AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 158
AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT90CAN128_AUTOMOTIVE PDF datasheet #2
- AT90CAN128_AUTOMOTIVE PDF datasheet #3
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14.9.2
14.9.3
158
AT90CAN32/64/128
Timer/Counter2 Register – TCNT2
Output Compare Register A – OCR2A
Table 14-4
rect PWM mode.
Table 14-4.
Note:
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
14-5.
Table 14-5.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
COM2A1
CS22
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See
page 153
shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
R/W
R/W
7
0
7
0
COM2A0
CS21
for more details.
0
0
1
1
0
0
1
1
0
1
0
1
R/W
R/W
6
0
6
0
Description
Normal port operation, OC2A disconnected.
Reserved
Clear OC2A on compare match when up-counting.
Set OC2A on compare match when downcounting.
Set OC2A on compare match when up-counting.
Clear OC2A on compare match when downcounting.
R/W
R/W
5
0
5
0
CS20
0
1
0
1
0
1
0
1
R/W
R/W
4
0
4
OCR2A[7:0]
0
TCNT2[7:0]
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
clk
clk
T2S
T2S
T2S
T2S
T2S
T
T
2
2
R/W
R/W
S
S
/256 (From prescaler)
/1024 (From prescaler)
3
0
3
0
/(No prescaling)
/8 (From prescaler)
/32 (From prescaler)
/64 (From prescaler)
/128 (From prescaler)
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
(1)
“Phase Correct PWM Mode” on
R/W
R/W
0
0
0
0
OCR2A
TCNT2
7682C–AUTO–04/08
Table
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