AT89S52 Atmel Corporation, AT89S52 Datasheet - Page 17

• Manufacturer Part Number: AT89S52
• Manufacturer: Atmel Corporation

Specifications of AT89S52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 4.0 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

Figure 12-1. Timer 2 in Clock-Out Mode
13. Interrupts
1919D–MICRO–6/08
(T2EX)
P1.0
P1.1
(T2)
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three
timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown
in
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that
write a 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Figure
OSC
TRANSITION
DETECTOR
13-1.
Table 13-1
÷2
EXEN2
shows that bit position IE.6 is unimplemented. User software should not
C/T2 BIT
EXF2
TR2
÷2
TIMER 2
INTERRUPT
(8-BITS)
RCAP2L RCAP2H
TL2
T2OE (T2MOD.1)
(8-BITS)
TH2
AT89S52
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