AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet - Page 28

• Manufacturer Part Number: AT89LP6440
• Manufacturer: Atmel Corporation

Specifications of AT89LP6440

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 5-5.
5.2.2
5.2.2.1
28
Symbol
DPU1
DPU0
DPD1
DPD0
SIGEN
DPS
DPCF = A2H
Not Bit Addressable
Bit
AT89LP3240/6440
Data Pointer Operating Modes
DPTR Redirect
Function
Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update
DPTR1 based on DPD1. If DPD1 = 0 the operation is post-increment and if DPD1 = 1 the operation is post-decrement.
When DPU1 = 0, DPTR1 is not updated.
Data Pointer 0 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR0 will also update
DPTR0 based on DPD0. If DPD0 = 0 the operation is post-increment and if DPD0 = 1 the operation is post-decrement.
When DPU0 = 0, DPTR0 is not updated.
Data Pointer 1 Decrement. When set, INC DPTR instructions targeted to DPTR1 will decrement DPTR1. When cleared,
INC DPTR instructions will increment DPTR1. DPD1 also determines the direction of auto-update for DPTR1 when
DPU1 = 1.
Data Pointer 0 Decrement. When set, INC DPTR instructions targeted to DPTR0 will decrement DPTR0. When cleared,
INC DPTR instructions will increment DPTR0. DPD0 also determines the direction of auto-update for DPTR0 when
DPU0 = 1.
Signature Enable. When SIGEN = 1 all MOVC @DPTR instructions and all IAP accesses will target the signature array
memory. When SIGEN = 0, all MOVC and IAP accesses target CODE memory.
Data Pointer Select. DPS selects the active data pointer for instructions that reference DPTR. When DPS = 0, DPTR will
target DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0.
DPCF
DPU1
7
– Data Pointer Configuration Register
The Dual Data Pointers on the AT89LP3240/6440 include three additional operating modes that
affect data pointer based instructions. These modes are controlled by bits in DSPR.
The Data Pointer Redirect to B bit, DPRB (DSPR.0), allows MOVX and MOVC instructions to
use the B register as the data source/destination when the instruction references DPTR1 as
shown in
multiple operands from different RAM locations.
Table 5-6.
DPU0
DPRB
6
0
0
1
1
Table 5-6
DPS
MOVX @DPTR Operating Modes
0
1
0
1
DPD1
5
and
Table
A, @DPTR0
A, @DPTR1
A, @DPTR0
B, @DPTR1
MOVX
MOVX
MOVX
MOVX
DPTR
DPD0
4
5-7. DPRB can improve the efficiency of routines that must fetch
MOVX A, @DPTR
SIGEN
A, @DPTR1
A, @DPTR0
B, @DPTR1
A, @DPTR0
3
Equivalent Operation for MOVX
/DPTR
MOVX
MOVX
MOVX
MOVX
0
2
@DPTR0, A
@DPTR1, A
@DPTR0, A
@DPTR1, B
MOVX
MOVX
MOVX
MOVX
DPTR
Reset Value = 0000 00X0B
MOVX @DPTR, A
–
1
@DPTR1, A
@DPTR0, A
@DPTR1, B
@DPTR0, A
3706C–MICRO–2/11
DPS
/DPTR
MOVX
MOVX
MOVX
MOVX
0