AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet

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AT89LP51RB2

Manufacturer Part Number
AT89LP51RB2
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89LP51RB2

Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP51RB2-20AAU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89LP51RB2-20AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89LP51RB2-20JU
Manufacturer:
Atmel
Quantity:
10 000
Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
Nonvolatile Program and Data Memory
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Conditions
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256 x 8 Internal RAM
– On-chip 1152KB Expanded RAM (ERAM)
– Dual Data Pointers
– 4-level Interrupt Priority
– 24KB/32KB of In-System Programmable (ISP) Flash Program Memory
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
– Enhanced UART with Automatic Address Recognition and Framing
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51IC2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44, PDIP40
– Configurable I/O Modes
– 2.4V to 5.5V V
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
Serial Bootloader
Error Detection
• Software Selectable Size (0, 256, 512, 768, 1024, or 1152 Bytes)
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
CC
Voltage Range
8-bit Flash
Microcontroller
with 24KB/32KB
Program
Memory
AT89LP51RB2
AT89LP51RC2
AT89LP51IC2
Summary
3722AS–MICRO–10/11

Related parts for AT89LP51RB2

AT89LP51RB2 Summary of contents

Page 1

... Quasi-bidirectional (80C51 Style), Input-only (Tristate) • Push-pull CMOS Output, Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40° 85°C Temperature Range – MHz @ 2.4V–5.5V (Single-cycle) 8-bit Flash Microcontroller with 24KB/32KB Program Memory AT89LP51RB2 AT89LP51RC2 AT89LP51IC2 Summary 3722AS–MICRO–10/11 ...

Page 2

... P1.6 8 (†SCK/CEX4/MOSI) P1.7 9 (DCL) RST 10 (RXD) P3.0 11 (SDA) P4.1 12 (TXD) P3.1 13 (INT0) P3.2 14 (INT1) P3.3 15 (T0) P3.4 16 (T1) P3.5 17 † SPI in remap mode ‡ AT89LP51ID2 Only AT89LP51RB2/RC2/IC2 Summary 2 1.3 44-pad VQFN/QFN/MLF † SPI in remap mode ‡ AT89LP51ID2 Only 33 P0.4 (AD4) (†MOSI/CEX2/MISO) P1.5 32 P0.5 (AD5) (†MISO/CEX3/SCK) P1.6 31 P0.6 (AD6) (†SCK/CEX4/MOSI) P1.7 30 P0.7 (AD7) (DCL) RST 29 POL (RXD) P3.0 28 P4.0 (SCL) (SDA) P4 ...

Page 3

... Pin Description Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description Pin Number VQFP VQFN PLCC PDIP Symbol RST P4.6 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary ...

Page 4

... Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description Pin Number VQFP VQFN PLCC PDIP Symbol GND POL P0.3 AT89LP51RB2/RC2/IC2 Summary ...

Page 5

... Atmel's high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set. The AT89LP51RB2/RC2/IC2 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock ...

Page 6

... The TWI and OCD features are not available on the PDIP package. The AT89LP51IC2 is also not available in PDIP. The features of the AT89LP51RB2/RC2/IC2 make it a powerful choice for applications that need pulse width modulation, high speed I/O, and counting capabilities such as alarms, motor control, corded phones, and smart card readers ...

Page 7

... Port 2 Configurable I/O Port 3 Configurable I/O Port 4 Configurable I/O Dual Analog Comparators Configurable Oscillator A Configurable Oscillator B (AT89LP51IC2) lists the fusible options for the AT89LP51RB2/RC2/IC2. These options maintain their RAM ERAM 256 Bytes 1152 Bytes Interface with 12-cycle Compatiblity UART Watchdog Timer Keyboard Interface Timer 0 ...

Page 8

... ALES EXRAM WS 1-0 XSTK ENBOOT AT89LP51RB2/RC2/IC2 Summary 8 User Configuration Fuses Description Selects between the High Speed Crystal Oscillator, Low Power Crystal Oscillator, External Clock on XTAL1A or Internal RC Oscillator for the source of the system clock when oscillator A is selected. Selects between the 32 kHzCrystal Oscillator, External Clock on XTAL1B or Internal RC Oscillator for the source of the system clock when oscillator B is selected (AT89LP51IC2 Only) ...

Page 9

... Reset The RST pin of the AT89LP51RB2/RC2/IC2 has selectable polarity using the POL pin (formerly EA). When POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST pin is active low with a pull-up resistor. For existing AT89C51RB2/RC2/IC2 sockets where EA is tied to VDD, replacing AT89C51RB2/RC2 with AT89LP51RB2/RC2/IC2 will main- tain the active high reset ...

Page 10

... I/O Ports The P0, P1, P2 and P3 I/O ports of the AT89LP51RB2/RC2/IC2 may be configured in four differ- ent modes. The default setting depends on the Tristate-Port User Fuse. When the fuse is set all the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode ...

Page 11

... Security The AT89LP51RB2/RC2/IC2 does not support the external access pin (EA). Therefore it is not possible to execute from external program memory in address range 0000H–1FFFH. When the third Lockbit is enabled (Lock Mode 4) external program execution is disabled for all addresses above 1FFFH. This differs from AT89C51RB2/RC2/IC2 where Lock Mode 4 prevents EA from being sampled low, but may still allow external execution at addresses outside the 8K internal space ...

Page 12

... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 3-1. Atmel AT89LP51RB2/RC2/IC2 SFR Map and Reset Values ...

Page 13

... CKCKON1 AFh Clock Control Register 1 (1) CKSEL 85h Clock Selection Register CLKREG AEh Clock Register (1) OSCCON 85h Oscillator Control Register Note: 1. Present on AT89LP51IC2 Only 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary RS1 – – – – – – – – ...

Page 14

... Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload AT89LP51RB2/RC2/IC2 Summary ET2 ES – – EADC ECMP IP1D PPCH PT2H PHS ...

Page 15

... Mnemonic Add Name SSCON 93h Synchronous Serial Control SSCS 94h Synchronous Serial Status SSDAT 95h Synchronous Serial Data SSADR 96h Synchronous Serial Address 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary TF1 TR1 TF0 TR0 GATE1 C/T1 M11 M01 TF2 EXF2 RCLK TCLK – ...

Page 16

... D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low Byte CH F9h PCA Timer/Counter High Byte CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 AT89LP51RB2/RC2/IC2 Summary KBLS7 KBLS6 KBLS5 KBLS4 KBE7 ...

Page 17

... ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0 CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary ECOM4 ...

Page 18

... AT89LP51RB2/RC2/IC2 Summary 18 Code # Range Flash Oscillators 24KB 1 Industrial (-40° 32KB 1 85° C) 32KB 2 for a cross reference between AT89C51RB2/RC2/IC2 and AT89LP51RB2/RC2/IC2 Package Types Ordering Code Package AT89LP51RB2-20AAU 44AA (LQFP) AT89LP51RB2-20AAUR AT89LP51RB2-20AU 44A (TQFP) AT89LP51RB2-20AUR AT89LP51RB2-20JU 44J (PLCC) AT89LP51RB2-20JUR AT89LP51RB2-20MU 44M1 (VQFN) AT89LP51RB2-20MUR ...

Page 19

... Cross Reference with AT89C51RB2/RC2/IC2 Table 4-1. Ordering Cross Reference AT89C51RB2/RC2/IC2 to AT89LP51RB2/RC2/IC2 Device Migration AT89C51RB2 to AT89LP51RB2 AT89C51RC2 to AT89LP51RC2 AT89C51IC2 to AT89LP51IC2 Table 4-2. Packages Not Found in AT89C51RB2/RC2/IC2 Device AT89C51RB2 to AT89LP51RB2 AT89C51RC2 to AT89LP51RC2 AT89C51IC2 to AT89LP51IC2 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary Package Packing Previous Ordering Code Stick ...

Page 20

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.102 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP51RB2/RC2/IC2 Summary TITLE 44AA, 44-lead Body Size, 1 ...

Page 21

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary BOTTOM VIEW COMMON DIMENSIONS ...

Page 22

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP51RB2/RC2/IC2 Summary 22 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 23

... VQFN/MLF D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary E Pin #1 Corner Pin #1 Option A 1 Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 ...

Page 24

... Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LP51RB2/RC2/IC2 Summary 24 D PIN 0º ~ 15º REF ...

Page 25

... Revision History Revision No. Revision A – October 2011 3722AS–MICRO–10/11 AT89LP51RB2/RC2/IC2 Summary History • Initial Release 25 ...

Page 26

... Atmel , Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’ ...

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