AT89LP213 Atmel Corporation, AT89LP213 Datasheet - Page 26

• Manufacturer Part Number: AT89LP213
• Manufacturer: Atmel Corporation

Specifications of AT89LP213

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

13.1.4
13.2
26
Port 1 Analog Functions
AT89LP213/214
Push-pull Output
Figure 13-4. Open-drain Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. Note that due to the 5V tolerant architecture, the push-pull output will have
reduced output high levels at DC operation and hot temperature. Under AC operation an inter-
grated boost circuit provides more source current. The push-pull port configuration is shown in
Figure
Figure
Figure 13-5. Push-pull Output
The AT89LP213/214 incorporates an analog comparator. In order to give the best analog perfor-
mance and minimize power consumption, pins that are being used for analog functions must
have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting
the port pins into the input-only mode as described in
inputs on P1.0 and P1.1 are disabled whenever the Analog Comparator is enabled by setting the
CEN bit in ACSR. CEN forces the PWD input on P1.0 and P1.1 low, thereby disabling the
Schmitt trigger circuitry. P1.0 and P1.1 will always default to input-only mode after reset regard-
less of the state of the Tristate-Port Fuse.
13-5. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see
13-3).
Register
From Port
From Port
Register
Input
Data
PWD
Input
Data
V
PWD
CC
“Port Configuration” on page
Port
Pin
3538E–MICRO–11/10
Port
Pin
24. Digital