AT89C55WD Atmel Corporation, AT89C55WD Datasheet - Page 9

• Manufacturer Part Number: AT89C55WD
• Manufacturer: Atmel Corporation

Specifications of AT89C55WD

• Flash (kbytes): 20 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 4.0 to 6.0
• Timers: 3
• Watchdog: Yes

6. Memory Organization
6.1
6.2
7. Hardware Watchdog Timer (One-time Enabled with Reset-out)
1921D–MICRO–6/08
Program Memory
Data Memory
The MCS-51 devices have a separate address space for Program and Data Memory. Up to
64 Kbytes each of external Program and Data Memory can be addressed.
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89C55WD, if EA is connected to V
4FFFH are directed to internal memory and fetches to addresses 5000H through FFFFH are to
external memory.
The AT89C55WD implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. That means the upper 128 bytes have the
same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used
in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H
(which is P2).
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the
following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT time-out period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
MOV 0A0H, #data
MOV @R0, #data
CC
, program fetches to addresses 0000H through
AT89C55WD
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