AT89C51RB2 Atmel Corporation, AT89C51RB2 Datasheet - Page 86

• Manufacturer Part Number: AT89C51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RB2

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 1.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Flash EEPROM
Memory
Features
Flash Programming and
Erasure
86
AT89C51RB2/RC2
The Flash memory increases EPROM and ROM functionality with in-circuit electrical
erasure and programming. It contains 16K or 32K Bytes of program memory organized
in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Pro-
grammable (ISP). ISP allows devices to alter their own program memory in the actual
end product under software control. A default serial loader (bootloader) program allows
ISP of the Flash.
The programming does not require external dedicated programming voltage. The nec-
essary high programming voltage is generated on-chip using the standard V
the microcontroller.
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The 16K or 32K Bytes Flash is programmed by Bytes or by pages of 128 Bytes. It is not
necessary to erase a Byte or a page before programming. The programming of a Byte
or a page includes a self erase before programming.
There are three methods of programming the Flash memory:
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Flash EEPROM internal program memory.
Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
Default loader in Boot ROM allows programming via the serial port without the need
of a user-provided loader.
Up to 64K Byte external program memory if the internal program memory is
disabled (EA = 0).
Programming and erase voltage with standard 5V or 3V V
Read/Programming/Erase:
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Typical programming time (32K Bytes) in 10 s
Parallel programming with 87C51 compatible hardware interface to programmer
Programmable security for the code in the Flash
100K write cycles
10 years data retention
First, the on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the UART.
Second, the Flash may be programmed or erased in the end-user application by
calling low-level routines through a common entry point in the Boot ROM.
Third, the Flash may be programmed using the parallel method by using a
conventional EPROM programmer. The parallel programming method used by
these devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the
AT89C51RB2/RC2. The bootloader and the Application Programming Interface
(API) routines are located in the BOOT ROM.
Byte-wise read without wait state
Byte or page erase and programming (10 ms)
CC
supply.
4180E–8051–10/06
CC
pins of