AT89C5115 Atmel Corporation, AT89C5115 Datasheet - Page 26

• Manufacturer Part Number: AT89C5115
• Manufacturer: Atmel Corporation

Specifications of AT89C5115

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Dual Data Pointer
Description
Application
26
AT89C5115
The T89C5115 implements a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are Seen by the CPU as DPTR and are accessed using the SFR
addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1
register (See Figure 18) is used to select whether DPTR is the data pointer 0 or the data
pointer 1 (See Figure 11).
Figure 11. Dual Data Pointer Implementation
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare…) are well served by
using one data pointer as a “source” pointer and the other one as a “destination” pointer.
Hereafter is an example of block move implementation using the two pointers and coded
in assembler. The latest C compiler takes also advantage of this feature by providing
enhanced algorithm libraries.
The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the
DPS bit in the AUXR1 register. However, note that the INC instruction does not directly
force the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move example, only the fact that DPS is toggled in the proper sequence mat-
ters, not its actual value. In other words, the block move routine works the same whether
DPS is 0 or 1 on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is
added
AUXR1EQU0A2h
move:movDPTR,#SOURCE ; address of SOURCE
mv_loop:incAUXR1; switch data pointers
end_move:
incAUXR1 ; switch data pointers
movDPTR,#DEST ; address of DEST
movxA,@DPTR; get a byte from SOURCE
incDPTR; increment SOURCE address
incAUXR1; switch data pointers
movx@DPTR,A; write the byte to DEST
incDPTR; increment DEST address
jnzmv_loop; check for NULL terminator
DPTR1
DPTR0
DPH0
DPH1
DPL0
DPL1
DPS
0
1
0
1
AUXR1.0
DPH
DPL
DPTR
4128G–8051–02/08