AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 137

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

8321A–MCU Wireless–10/11
 Bit 7 - ANT_SEL
Signals selected antenna, related to the last received frame.
Table 11-10. ANT_SEL.
Register Bits
ANT_SEL
Note:
This register bit signals the currently selected antenna path. The selection may be
based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of
register bits ANT_CTRL, for details refer to
 Bit 3 - ANT_DIV_EN
The register bit ANT_DIV_EN activates the autonomous Antenna Diversity algorithm.
Table 11-11. ANT_DIV_EN.
Register Bits
ANT_DIV_EN
Note:
If register bit ANT_DIV_EN is set the Antenna Diversity algorithm is enabled. On
reception of a frame the algorithm selects an antenna autonomously during SHR
search. This selection is kept until:
 A new SHR search starts
 Leaving receive states
 Register bits ANT_CTRL are manually programmed
 Bit 2 - ANT_EXT_SW_EN
The register bit ANT_EXT_SW_EN controls the external antenna switch.
Table 11-12. ANT_EXT_SW_EN.
Register Bits
ANT_EXT_SW_EN
If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential
control signal for an Antenna Diversity switch. The selection of a specific antenna is
done either by the automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or
according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled.
If the Atmel AT86RF232 is not in a receive or transmit state, it is recommended to
disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid
leakage current of an external RF switch, especially during SLEEP state. If register bit
ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground.
Pin 10 (DIG2) is overloaded with RX and TX Frame Time Stamping, see
IRQ_2_EXT_EN is set.
1.
1.
If the autonomous Antenna Diversity algorithm is enabled, the register bit
ANT_SEL maintains its previous value (from the last received frame) until a new
SHR has been found.
If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to one, too. This is
not automatically done by the hardware.
Value
Value
Value
0
1
0
1
0
1
Description
Antenna 0
Antenna 1
Description
Antenna Diversity algorithm is disabled
Antenna Diversity algorithm is enabled
Description
Antenna Diversity RF switch control is disabled
Antenna Diversity RF switch control is enabled
Section
11.3.2.
AT86RF232
Section
11.4, if
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