AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 33

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.9.1.12
3.9.1.13
3.9.1.14
3.9.1.15
32002F–03/2010
ITLB Miss Exception
Instruction Address Exception
ITLB Protection Exception
Breakpoint Exception
The Instruction Address Error exception is generated if the generated instruction memory
address has an illegal alignment.
The ITLB Miss exception is generated when the MPU is enabled and the instruction memory
access does not hit in any regions. Used only if an MPU is present.
The ITLB Protection exception is generated when the instruction memory access violates the
access rights specified by the protection region in which the address lies. Used only if an MPU is
present.
The Breakpoint exception is issued when the OCD breakpoint input line to the CPU is aseerted,
and SREG[DM] is cleared.
When entering the exception routine, RAR_DBG points to the breakpoint instruction, and the
CPU will enter Debug mode. An external debugger can optionally assume control of the CPU
when the Breakpoint Exception is executed. The debugger can then issue individual instructions
to be executed in Debug mode. Debug mode is exited with the retd instruction. This passes con-
trol from the debugger back to the CPU, resuming normal execution.
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x14;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x50;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x18;
RSR_DBG = SR;
RAR_DBG = PC;
SR[M2:M0] = B’110;
SR[D] = 1;
SR[DM] = 1;
SR[EM] = 1;
SR[GM] = 1;
SYS
SYS
SYS
SYS
SYS
SYS
) = PC;
) = SR;
) = PC;
) = SR;
) = PC;
) = SR;
AVR32
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