AT32UC3C0512C Atmel Corporation, AT32UC3C0512C Datasheet - Page 37
AT32UC3C0512C
Manufacturer Part Number
AT32UC3C0512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512C
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.9.1.26
3.9.1.27
3.9.1.28
3.10
32002F–03/2010
Interrupt latencies
Floating-point Exception
Coprocessor Absent Exception
Supervisor call
Unused in AVR32UC.
The Coprocessor Absent exception is generated when a nonexisting coprocessor is addressed
by a coprocessor instruction. Used only if one or more coprocessors are present. Executing
coprocessor instructions in systems with no coprocessors results in an Unimplemented Instruc-
tion exception instead.
Supervisor calls are signalled by the application code executing a supervisor call (scall) instruc-
tion. The scall instruction behaves differently depending on which context it is called from. This
allows scall to be called from other contexts than Application.
When the exception routine is finished, execution continues at the instruction following scall. The
rets instruction is used to return from supervisor calls.
The following features in AVR32UC ensure low and deterministic interrupt latency:
• Four different interrupt levels and an NMI ensures that the user can efficiently prioritize the
• Long-running instructions such as ldm, stm, pushm, popm, divs and divu will be aborted if an
• Interrupts are autovectored, allowing the CPU to jump directly to the interrupt handler.
• When an interrupt of level m is received, the CPU will start stacking register file registers,
interrupt sources.
interrupt request is received. The slowest instruction that can not be aborted by a pending
interrupt has a worst case issue latency of 5 cycles. This implies that an interrupt request will
need to wait at most 5 cycles for an instruction to complete. The fastest instructions need
only a single cycle to complete.
return address and status register. After this stacking is performed, the CPU will jump to the
autovector address of the interrupt of level m. If an interrupt of level n, where n > m, is
received during this stacking, the CPU will jump to the autovector address of the interrupt of
level n, NOT the autovector address of the original interrupt.
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x30;
If ( SR[M2:M0] == {B’000 or B’001} )
else
*(--SP
*(--SP
PC ← EVBA | 0x100;
SR[M2:M0] ← B’001;
LR ← PC + 2;
PC ← EVBA | 0x100;
SYS
SYS
SYS
SYS
) = PC;
) = SR;
) = PC;
) = SR;
AVR32
37