AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 82
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AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
8.12
8.13
8.14
32002F–03/2010
Branch instructions
Call instructions
Return from execution mode instructions
The branch instructions cause a pipeline flush and change-of-flow if taken. Two cycles must be
added to the issue latency if the branch is taken.
Table 8-9.
Call instructions behave similarly to branches, except that the link register (LR) must be
updated. The issue latency presented in the table includes the branch penalty.
The breakpoint instruction takes a single cycle if Debug mode is disabled, in this case it exe-
cutes as a nop. The breakpoint instruction updates RAR_DBG instead of LR.
Table 8-10.
The rete and rets instruction may pop the status register and return address from the system
stack, and perform a branch to the return address. The retd instruction gets the return address
and return status registers from the RAR_DBG and RSR_DBG system registers. The issue
latency presented in the table includes the branch penalty.
Mnemonics
br{cond3}
br{cond4}
rjmp
ret{cond4}
Mnemonics
acall
icall
mcall
rcall
scall
sscall
breakpoint
Branch instructions
Call instructions
C
E
C
C
C
C
E
C
E
C
C
C
Operands
disp
disp
disp
Rs
Operands
disp
Rd
Rp[disp]
disp
disp
Description
Branch if condition satisfied.
Relative jump.
Conditional return from subroutine with move
and test of return value.
Description
Register indirect call.
Memory call.
Relative call.
Secure State call. CPU revision 3 and higher
only.
Application call
Supervisor call
Breakpoint.
AVR32
Issue
latency
4
4
4
4
4
6
5
3
Issue
latency
1
1
1
1
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