AT32UC3B1512 Atmel Corporation, AT32UC3B1512 Datasheet - Page 372
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AT32UC3B1512
Manufacturer Part Number
AT32UC3B1512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1512
Flash (kbytes)
512 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1512-Z1UT
Manufacturer:
ROHM
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 372 of 684
- Download datasheet (11Mb)
22.7.2.11
32059L–AVR32–01/2012
Management of control endpoints
•Special considerations for control endpoints
•STALL handshake and retry mechanism
•Overview
•Control write
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are
cleared. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in
UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these
endpoints. When read, their value are always zero.
Control endpoints are managed using:
Figure 22-15 on page 373
ler will not necessarily send a NAK on the first IN token:
• The RXSTPI bit which is set when a new SETUP packet is received and which shall be
• The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared
• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to
• If the user knows the exact number of descriptor bytes that must be read, it can then
• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the
cleared by firmware to acknowledge the packet and to free the bank.
by firmware to acknowledge the packet and to free the bank.
accept a new IN packet and which shall be cleared by firmware to send the packet.
anticipate the status stage and send a zero-length packet after the next IN token.
bytes have been sent by the host and that the transaction is now in the status stage.
shows a control write transaction. During the status stage, the control-
372
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