AT32UC3B1256 Atmel Corporation, AT32UC3B1256 Datasheet - Page 11
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AT32UC3B1256
Manufacturer Part Number
AT32UC3B1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUR
Manufacturer:
OMRON
Quantity:
12 000
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
7745C–AVR32–05/09
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From the application point of view, if all the rules described in this document are followed, the
state of the MCU when the application begins to execute at 80002000h will be the same as after
the last MCU hardware reset that occurred (whatever its causes) except that:
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If the ISP_FORCE GP fuse bit is 0 and the user has set the ISP_IO_COND_EN GP fuse bit
to 0, the ISP will no longer be reachable, except if the programmed application sets the
ISP_FORCE GP fuse bit to 1.
If the ISP_IO_COND_EN GP fuse bit is 1, but the bootloader configuration word is corrupted
(wrong CRC8) or has an invalid boot key or GPIO pin, the USB DFU ISP is systematically
launched to allow the user to correct this value.
Figure 6-2 mentions the ISP RAM key. It is a specific value written in the first word of the
INTRAM by the bootloader. This key is manipulated only by the boot process for its internal
behavior to know whether it is a warm boot following the execution of the USB DFU ISP. All
the user has to know about this key is that setting the first word of the INTRAM to
4953504Bh (“ISPK”) will alter the behavior of the bootloader after a subsequent reset, so it is
recommended that applications leave the first word of the INTRAM unused thanks to an
appropriate linker script (the C99 standard requires that a null pointer compares unequal to
a pointer to any object or function).
See the AVR UC3 datasheets referred to by Section 3 for a detailed description of the MCU
reset causes.
The Cycle Counter system register will have counted a few cycles.
The Brown-Out Detector may be activated, according to Figure 6-2.
The Power Manager registers may indicate some activity for Osc0 or PLL0 if the application
is launched from the ISP without reset.
The USB register bit-fields that are not reset when disabling the USB macro may not contain
their respective reset values if the application is launched from the ISP without reset.
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