AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 155

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10. Revision History
32002F–03/2010
Doc. Rev.
32002F
32002E
32002D
32002C
32002B
32002A
Date
2009-08-01
2007-11-19
2007-03-30
2010-03-12
2009-09-01
2007-08-03
Comments
Improved description of events and priority.
Replaced invalid reference in the OCD.PDBG register.
Note added about overall system interrupt latency.
Added MSU system registers.
Added Floating-Point hardware description.
Added OCD DCCPU and DCEMU interrupts.
Added PDBG register for individual module masks.
Added AVR32 architecture revision 3 secure state support.
COUNT/COMPARE system register reset-on-match now programmable by CPUCR
Corrected LDM, STM, and SCALL instruction cycle count in cycle count chapter.
Corrected maximum IRQ latency in the Pipeline chapter.
MPU compilant with revision 2 of AVR32 Architecture.
Added cycle counts for new instruction in version 2 of the CPU.
Added COUNT/COMPARE system register reset-on-match.
Added CPU Local Bus.
Reconfigured OCD AXC register.
Added Memory Service Unit (MSU) description. Added description of peripheral behavior
in Debug.
Initial revision.
AVR32
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