AT32UC3B0128AU Atmel Corporation, AT32UC3B0128AU Datasheet - Page 13

• Manufacturer Part Number: AT32UC3B0128AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0128AU

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.3 Customizing the ISP Configuration Word
7.3.1 Step 1: Setting the ISP_BOOT_KEY Field
7.3.2 Step 2: Setting the ISP_IO_COND_LEVEL Field
7.3.3 Step 3: Setting the ISP_IO_COND_PIN Field
7.3.4 Step 4: Setting the ISP_CRC8 Field
7.3.5 Step 5: Program the Configuration Word in the User Page
7.3.5.1 Using avr32program
7745C–AVR32–05/09
Once the ISP is activated, it establishes a USB connection with the connected PC. It may take a
few seconds because of the autobaud that is performed using the USB starts of frames to deter-
mine the frequency of the clock input on Osc0. Trying to communicate with the ISP before it is
detected by the PC OS as a USB device will fail.
The purpose of this section is to propose a method to compute the ISP Configuration Word for a
given set of (ISP_IO_COND_PIN, ISP_IO_COND_LEVEL) values (Refer to section 6.2.2 “Flash
User Page” for a description of the ISP Configuration Word stored in Flash).
As mentionned in Table 6-4. the ISP_BOOT_KEY field must always be set to 0x494F at offset
17. At this step, the configuration word is always 0x929E**** (with bit 16 unset).
As mentionned in Table 6-4. the ISP_IO_COND_LEVEL field is either high (1) or low (0) set at
bit 16 of the ISP configuration word.
For a high level condition, the ISP configuration word is always 0x929F****.
For a low level condition, the ISP configuration word is always 0x929E****.
As mentionned in Table 6-4. the ISP_IO_COND_PIN field is placed at offset 8 of the ISP config-
uration word and contains the GPIO pin number the boot process will test.
As an example, we’ll use PX16 on AT32UC3A0512 (i.e. QFP144 pin 61 so GPIO pin 88 (i.e.
0x58 in hexadecimal representation) and assume a high level condition (cf step 2): the ISP con-
figuration word is then 0x929F58**.
As mentionned in Table 6-4. the ISP_CRC8 value is the CRC of the three other Bytes of the ISP
configuration word.
Using the example from step 3, the CRC8 of 0x929F58 is 0xD2. The ISP configuration word
should then be 0x929F58D2.
There are several methods to compute a CRC8 and several resources on the web available for
t h i s
http://www.smbus.org/faq/crc8Applet.htm, fill in the “Enter hex-coded message...” field with
929F58, press the OK button, then read the “Frame Check Sequence...” field that contains the
CRC8 value (“Frame Check = 0xd2”).
•
•
Create a binary file made of one 32bit word with the value 0x929F58D2; name that binary
file e.g. isp_mycfg.bin
Issue the following command through a hardware debugger (such as the JTAG-ICE mkII or
the AVR ONE!):
avr32program program -finternal@0x80000000,512Kb -cxtal -e -v -O0x808001FC -Fbin
isp_mycfg.bin
p u r p o s e .
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