AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 66
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0128-A2UT
Manufacturer:
XILINX
Quantity:
150
Company:
Part Number:
AT32UC3B0128-U
Manufacturer:
ATMEL
Quantity:
9 500
Company:
Part Number:
AT32UC3B0128-U
Manufacturer:
ATMEL
Quantity:
1 400
Part Number:
AT32UC3B0128-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT32UC3B0128-Z2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
32059L–AVR32–01/2012
- Processor and Architecture
7. TC
8. Channel chaining skips first pulse for upper channel
1. LDM instruction with PC in the register list and without ++ increments Rp
2. RETE instruction does not clear SREG[L] from interrupts
3. Privilege violation when using interrupts in application mode with protected system
4. USART
5. ISO7816 info register US_NER cannot be read
6. ISO7816 Mode T1: RX impossible after any TX
7. The RTS output does not function correctly in hardware handshaking mode
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
The NER register always returns zero.
Fix/Workaround
None.
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
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