AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 297
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Price
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21. Universal Synchronous Asynchronous Receiver Transmitter (USART)
21.1
21.2
32059L–AVR32–01/2012
Features
Overview
Rev: 4.0.0.6
•
•
•
•
•
•
•
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The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides a full
duplex, universal, synchronous/asynchronous serial link. Data frame format is widely configu-
rable, including basic length, parity, and stop bit settings, maximizing standards support. The
receiver implements parity-, framing-, and overrun error detection, and can handle un-fixed
frame lengths with the time-out feature. The USART supports several operating modes, provid-
ing an interface to RS485 and SPI buses, with ISO7816 T=0 and T=1 smart card slots, infrared
transceivers, and modem port connections. Communication with slow and remote devices is
eased by the timeguard. Duplex multidrop communication is supported by address and data dif-
ferentiation through the parity bit. The hardware handshaking feature enables an out-of-band
flow control, automatically managing RTS and CTS pins. The Peripheral DMA Controller con-
nection enables memory transactions, and the USART supports chained buffer management
without processor intervention. Automatic echo, remote-, and local loopback -test modes are
also supported.
Configurable baud rate generator
5- to 9-bit full-duplex, synchronous and asynchronous, serial communication
RS485 with line driver control
ISO7816, T=0 and T=1 protocols for Interfacing with smart cards
IrDA modulation and demodulation
SPI Mode
Test Modes
Supports two Peripheral DMA Controller channels
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generation and error detection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency over-sampling by 8 or 16 times
– Optional RTS-CTS hardware handshaking
– Optional DTR-DSR-DCD-RI modem signal management
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
– , NACK handling, and customizable error counter
– Communication at up to 115.2Kbit/s
– Master or slave
– Configurable serial clock phase and polarity
– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency
– Automatic echo, remote- and local loopback
– Buffer transfers without processor intervention
297
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