AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 643
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 643 of 1012
- Download datasheet (16Mb)
26.7.2.18
26.7.2.19
32072G–11/2011
CRC error
Interrupts
•Global interrupts
•Endpoint interrupts
For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token
(among 3) is well received by the USBB, then the two last banks will be discarded.
This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI)
bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE)
bit is one.
A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The
OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
The exception device global interrupts are:
The processing device endpoint interrupts are:
The exception device endpoint interrupts are:
• The Suspend (SUSP) interrupt
• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number
• The Micro Start of Frame (MSOF) interrupt with no CRC error.
• The End of Reset (EORST) interrupt
• The Wake-Up (WAKEUP) interrupt
• The End of Resume (EORSM) interrupt
• The Upstream Resume (UPRSM) interrupt
• The Endpoint n (EPnINT) interrupt
• The DMA Channel n (DMAnINT) interrupt
• The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one)
• The Micro Start of Frame (MSOF) interrupt with a CRC error
• The Transmitted IN Data Interrupt (TXINI)
• The Received OUT Data Interrupt (RXOUTI)
• The Received SETUP Interrupt (RXSTPI)
• The Short Packet (SHORTPACKET) interrupt
• The Number of Busy Banks (NBUSYBK) interrupt
• The Received OUT isochronous Multiple Data Interrupt (MDATAI)
• The Received OUT isochronous DataX Interrupt (DATAXI)
• The Underflow Interrupt (UNDERFI)
CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)
Figure 26-6 on page
625.
643
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