AT32UC3A3256 Atmel Corporation, AT32UC3A3256 Datasheet - Page 38
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AT32UC3A3256
Manufacturer Part Number
AT32UC3A3256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A3256-ALU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A3256-ALUR
Manufacturer:
ATMEL
Quantity:
1 500
Company:
Part Number:
AT32UC3A3256-ALUT
Manufacturer:
TST
Quantity:
430
Part Number:
AT32UC3A3256-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
AT32UC3A3256-CTUT
Manufacturer:
ATMEL
Quantity:
2 757
Company:
Part Number:
AT32UC3A3256-U
Manufacturer:
ATMEL
Quantity:
89
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
3.10.1
3.10.2
3.11
32002F–03/2010
NMI latency
Maximum interrupt latency
Minimum interrupt latency
Note that the overall system latency from an interrupt request is signaled to the request is being
handled depends on a number of things in addition to the latency through the CPU. The latency
through the interrupt controller will affect interrupt latency for all peripheral interrupt requests and
the bus matrix, code and data memories will affect overall responsiveness.
The maximum CPU interrupt latency can be calculated as follows:
Table 3-7.
The minimum CPU interrupt latency of an interrupt request of level m will occur when the CPU is
in the process of stacking the registers and return address associated with an interrupt request
of level n, where n < m. If the level m interrupt request arrives just as the CPU is about to jump to
the autovector address for the interrupt of level n, the CPU will jump directly to the autovector
address of the latest arriving interrupt. In this case, the minimum interrupt latency is as follows:
Table 3-8.
Assuming that the interrupt request arrives when the CPU is in the process of executing program
code, the minimum interrupt latency can be calculated as follows:
Table 3-9.
Non-maskable interrupts (NMI) behave similarly to interrupts, except that they do not automati-
cally push register file registers on the stack. NMI can, similar to interrupts, abort long-running
instructions.
Source
Wait for the slowest instruction to complete
Stack register file registers, return address and status register, and jump to
autovector target
Wait for autovector target instruction to be fetched
TOTAL
Source
Jump to autovector target
Wait for autovector target instruction to be fetched
TOTAL
Source
Wait for the fastest instruction to complete
Stack register file registers, return address and status register, and jump to
autovector target
Wait for autovector target instruction to be fetched
TOTAL
Maximum interrupt latency
Minimum interrupt latency - higher priority interrupt preempts lower priority
interrupt
Minimum interrupt latency - interrupt received when executing program code
Delay
6
10
1
17
Delay
1
1
2
Delay
1
10
1
12
AVR32
38