AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 69
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
7.2.1.3
7.2.1.4
7.2.1.5
7.2.1.6
7.2.2
7.2.2.1
32002F–03/2010
MPU exception handling
MPU Cacheable Register A / B- MPUCRA / MPUCRB
MPU Bufferable Register A / B- MPUBRA / MPUBRB
MPU Access Permission Register A / B - MPUAPRA / MPUAPRB
MPU Control Register - MPUCR
ITLB Protection Violation
The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre-
sponding bit is set, the region is cacheable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUCR registers.
The MPUBR registers have one bit per region, indicating if the region is bufferable. If the corre-
sponding bit is set, the region is bufferable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUBR registers.
The MPUAPR registers indicate the access permissions for each region. The MPUAPR is writ-
ten to 0 upon reset. The possible access permissions are shown in
Table 7-3.
The MPUCR controls the operation of the MPU. The MPUCR has only one field:
This chapter describes the exceptions that can be signalled by the MPU.
An ITLB protection violation is issued if an instruction fetch violates access permissions. The vio-
lating instruction is not executed. The address of the failing instruction is placed on the system
stack.
AP
B’0000
B’0001
B’0010
B’0011
B’0100
B’0101
B’0110
B’0111
B’1000
B’1001
B’1010
Other
• E - Enable. If set, the MPU address checking is enabled. If cleared, the MPU address
checking is disabled and no exceptions will be generated by the MPU.
Access permissions implied by the APn bits
Privileged mode
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
Read / Write
Read / Write / Execute
Read / Write
Read / Write
None
UNDEFINED
Unprivileged mode
None
None
None
None
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
None
UNDEFINED
Table 7-3 on page
AVR32
69.
69