AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 91

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058KS–AVR32–01/12
15.5.11
15.5.12
15.5.13
ABDAC
FLASHC
RTC
1. Audio Bitstream DAC is not functional.
1. The address of Flash General Purpose Fuse Register Low (FGPFRLO) is 0xFFFE140C
2. The command Quick Page Read User Page(QPRUP) is not functional.
3. PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0]
4. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,
1. Writes to control (CTRL), top (TOP) and value (VAL) in the RTC are discarded if the
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
Fix/Workaround
Do not use the ABDAC on revE.
on revE instead of 0xFFFE1410.
Fix/Workaround
None.
Fix/Workaround
None.
on revision E instead of WriteData[7:0], ByteAddress[2:0].
Fix/Workaround
None.
EP, EA, WUP, EUP commands may happen
- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a
given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the
other half of the flash may fail. This may lead to an exception or to other errors derived from
this corrupted read access.
- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may
fail. This may lead to an exception or to other errors derived from this corrupted read access.
- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading
(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to
an exception or to other errors derived from this corrupted read access.
Fix/Workaround
Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or
through the EBI. After these commands, read twice one flash page initialized to 00h in each
half part of the flash.
RTC peripheral bus clock (PBA) is divided by a factor of four or more relative to the
HSB clock.
Fix/Workaround
Do not write to the RTC registers using the peripheral bus clock (PBA) divided by a factor of
four or more relative to the HSB clock.
AT32UC3A
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