AT32UC3A0512AU Atmel Corporation, AT32UC3A0512AU Datasheet - Page 80
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AT32UC3A0512AU
Manufacturer Part Number
AT32UC3A0512AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0512AU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
32058KS–AVR32–01/12
15.4
15.4.1
15.4.2
15.4.3
Rev. H
PWM
ADC
SPI
1. PWM channel interrupt enabling triggers an interrupt
2. PWM counter restarts at 0x0001
3. PWM update period to a 0 value does not work
1. Sleep Mode activation needs additional A to D conversion
1. SPI Slave / PDCA transfer: no TX UNDERRUN flag
2. SPI FDIV option does not work
3. SPI disable does not work in SLAVE mode.
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1
Fix/Workaround
Read the last received data, then perform a Software Reset.
AT32UC3A
80