MC68SC302PU20 Motorola, MC68SC302PU20 Datasheet
MC68SC302PU20
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MC68SC302PU20 Summary of contents
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... MOTOROLA MC68SC302 Passive ISDN Protocol Engine User's Manual ...
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... ISDN basic rate interface. The three SCCs support two 64kbit per second B-channels and one 16kbit per second D-channel. The 68SC302 connects gluelessly to Motorola’s MC145572 U transceiver or MC145574 S/T transceiver and added bonus, eliminates the need for a second oscillator for the transceiver chip ...
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... Bytes FIFO for B1 and B2 Channel (Rx/Tx) • Bytes FIFO for D Channel (Rx/Tx) — Glueless Interface to Motorola and Other Popular ISDN S/T and U Interface Chips — Supports Motorola Interchip Digital Link (IDL) — Supports General Circuit Interface (GCI), Also Known as IOM-2 TM IOM trademark of Siemens Corporation ...
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... B channel per direction and 64 bytes per direction for the D channel. This provides 32msec worth of basic rate data to be stored in the buffers, allowing ample interrupt latency time for host platform operating systems. The IDL or GCI interface provides direct connection to the Motorola MC145572 U interface transceiver, the MC145574 S/T MOTOROLA 2 ...
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... Card Information Structure (CIS): 1)The CIS can 1-4 PIO AND INTERRUPT PINS 1536 BYTE RAM SCC2 2 SMCs SCC3 IDL/GCI INTERFACE IDL/GCI PINS MC68SC302 USER’S MANUAL PIO AND INT I/F ISA PnP/ PCMCIA ISA PnP INTERFACE PCMCIA INTERFACE INTERFACE SCP 2 SCP/E PROM INTERFACE MOTOROLA ...
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... Figure 1-2. Passive NT1 TA Block Diagram Figure 1-3 shows a basic rate terminal adaptor with the 4-wire S/T interface. This architecture is almost identical to the U interface TA with the exception that the TA clock source is provided to the S/T transceiver from the MC68SC302. MOTOROLA IDL OR GCI BUS MC68SC302 20.048 MHZ CLOCK ISA BUS MC68SC302 USER’ ...
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... Figure 1-4. NT1 TA Block Diagram with POTS Interface and Datapump Figure 1-5 shows a PC Card TA based on the SC302. 1-6 IDL OR GCI BUS MC68SC302 15.36 MHZ CLOCK 15.36 MHZ ISA BUS 20.048 MHZ CLOCK IDL OR GCI BUS PIO DATAPUMP MC145480 ISA BUS MC68SC302 USER’S MANUAL 145574 S/T I/F LINE I/F 20.048 MHZ LINE I/F 145572 U I/F LINE I/F POTS I/F MOTOROLA ...
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... SC302 pins for customer daughter cards. This includes access to the ISA/PCMCIA bus pins. • Options for three types of serial EEPROM for the PCMCIA or ISA Configuration. Figure 1-6 shows the ADS block diagram. MOTOROLA IDL OR GCI BUS MC68SC302 20.048 MHZ CLOCK Figure 1-5. PC Card TA MC68SC302 USER’ ...
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... MC68SC302 Overview 2 WIRE S/T INTERFACE U INTERFACE MOTOROLA MC145572 MOTOROLA MC145574 S/T INTERFACE U INTERFACE IDL/GCI SCP MC68SC302 1-8 CIS/PnP EEPROM 4 WIRE X25080 SOCKET PCMCIA BUS CONNECTOR Figure 1-6. ADS Block Diagram MC68SC302 USER’S MANUAL CIS/PnP CIS/PnP EEPROM EEPROM ST95020 93C46 SOCKET SOCKET SCP 128-PIN EXPANSION ...
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... The host bus interface has two groups, the ISA interface and the PCMCIA interface. All groups are then organized into functional groups and described in the following sections. For more detail on each signal, refer to the paragraph named for that signal. MOTOROLA MC68SC302 USER’S MANUAL 2-1 ...
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... BUS CONTROL MC68SC302 IOR / PC_E2E IOW / PC_MODE MEMR / PC_OE MEMW / PC_WE IRQ3 / PC_READY/ PC_IREQ IRQ4/ IOCS16 / PC_STSCHG IRQ5 / IOCHRDY / PC_WAIT IRQ7 / MEMCS16 / PC_CISCS 4 IRQ[9,10,11,12] / IRQSEL[3:0] IRQ15 / IRQO SBHE / PC_CE2 REF / PC_REG AEN / PC_A25 BALE / PC_CE1 RESET MC68SC302 USER’S MANUAL MOTOROLA ...
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... CMOS levels. CLKOUT supplies a CMOS level output. All ISA output pins (except CLKOUT) can drive up to 120pF with 24mA IOL. All peripheral output pins can drive up to 100pF. CLKOUT is designed to drive up to 50pF. MOTOROLA Signal Description and Pin Control MNEMONIC ...
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... SBHE—SYSTEM BUS HIGH ENABLE. This input signal controls the flow of data on the data bus. When the MC68SC302 is used in a 16-bit data bus mode, this pin, when low, enables driving data on the high half of the data bus. 2-4 MC68SC302 USER’S MANUAL MOTOROLA ...
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... The MC68SC302 uses this signal to disable any possibility of driving the data bus. 2.1.3.12 RESET — RESET. This active high input pin starts an initialization sequence that resets the entire device with all internal peripherals. The on-chip system RAM is not ini- MOTOROLA Signal Description and Pin Control MC68SC302 USER’S MANUAL 2-5 ...
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... Characteristics. A valid clock signal oscillates between a low voltage of between GND – 0.3 and 0.6 volts and a high voltage of between 4.0 and V 2.1.5.2 XTAL— CRYSTAL OUTPUT. This output connects the on-chip oscillator output to an external crystal external clock is used, XTAL should be left unconnected. 2-6 NOTE volts. CC MC68SC302 USER’S MANUAL MOTOROLA ...
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... Card Is Ready (Memory mode) / Interrupt request in Memory+IO mode Reset Parallel Port Select Pins [3-0] Crystal Oscillator Clock Clock Out Power System Power Supply and Return MOTOROLA Signal Description and Pin Control NOTE MNEMONIC I/O 2.2.1.2 Address Bus Pins. PC_A[16:0]–PCMCIA PC_A[16:0] I PC_A[23:17]/ I 2.2.1.1 PC_A[21:17]/IRQIN[5:1]/PA[15:12]—PCM- ...
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... In memory+IO mode (selected in the COR), this output can be programmed to indicate changes in the RDY/BSY pin or in the ring indication input. For more details, please refer to the PCMCIA interface definition. 2-8 output MC68SC302 USER’S MANUAL group of is asserted by the memory MOTOROLA ...
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... If an external clock is used, XTAL should be left unconnected. 2.2.4.3 CLKO— CLOCK OUT. This output clock signal is derived from the on-chip clock oscillator. The frequency of the CLKO signal is programmable and also can be disabled. CLKO supports both CMOS and TTL output levels. MOTOROLA Signal Description and Pin Control NOTE volts. ...
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... PA11 SPRXD SPTXD SPCLK E2EN / PA0 IRQIN5 / SCPEN1 / PA1 IRQIN6 / SCPEN2 / PA2 SCPEN3 / PA3 MC68SC302 USER’S MANUAL I/O SECTION 2.3.1 ISDN Pins I/O O I/O I/O O I/O I 2.3.2 NMSI Pins I I I 2.3.3 SCP Pins I/O 2.3.3 SCP Pins I O I/O O I/O MOTOROLA ...
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... SDS1 / FSYN / IRQIN2—SERIAL DATA STROBE 1 / CODEC FRAME SYNC / INTERRUPT REQUEST IN 2 PIN. This bidirectional signal is used as the ISDN serial data strobe output or a Codec frame synchronization signal interrupt request 2 input. MOTOROLA Signal Description and Pin Control MC68SC302 USER’S MANUAL ...
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... The SC302 has many multi-function I/O pins.These pins function varies according to the se- lected operation mode, i.e. PCMCIA or ISA in addition to programming in the control regis- ters. Some pins have a parallel I/O port capability, so they can be used as general-purpose I/O pins or as dedicated peripheral interface pins. 2-12 MC68SC302 USER’S MANUAL MOTOROLA ...
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... I/O pin, then the input to the peripheral is automatically connect- or GND, based on the pin's function. This does not affect the operation ed internally the port pins in their general-purpose I/O function. MOTOROLA Signal Description and Pin Control MC68SC302 USER’S MANUAL 2-13 ...
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... IRQIN1 =1 , CLKRx =0 IRQIN2=1 IRQIN3=1 IRQIN4 = IRQIN2 =1 , A20=0 IRQIN3 =1 , A21=0 IRQIN4 =1 , A22=0 IRQIN5 =1 , A23=0 $81E PA5 PA4 PA3 PA2 PA1 $820 PA5 PA4 PA3 PA2 PA1 $822 PD5 PD4 PD3 PD2 PD1 MOTOROLA 0 PA0 0 PA0 0 PD0 ...
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... Other pins that are not muxed with parallel I/O pins are controlled by the PMFSR 0-6 bits. Their functionality is described in the following table. 2-15 Port A SCP Enable Control (PENCR SPNL3 SPNL2 SPNL1 MC68SC302 USER’S MANUAL $826 RSVD SCPEN3 SCPEN2 SCPEN1 RSVD MOTOROLA ...
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... MC68SC302 USER’S MANUAL INPUT TO PERIPHERAL PMFS BIT = 1 IRQIN1 A19=0, IRQIN1 = CLKRx IRQIN1 =1, CLKRx =0 SDS1/FSYN*** IRQIN2=1 SDS2 IRQIN3=1 RI IRQIN4 A20 IRQIN2 =1, A20=0 A21 IRQIN3 =1, A21=0 A22 IRQIN4 =1, A22=0 A23 IRQIN5 =1, A23 PA5 PA4 PA3 PA2 PA1 MOTOROLA $824 0 PA0 0 ...
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... Interrupt masking is accomplished by programming the Interrupt Mask Register (IMR). Each bit in the IMR corresponds to one of the interrupt sources. When a masked interrupt source has a pending interrupt request, the corresponding bit is set in the Interrupt Pending Register (IPR), even though the interrupt will not reach the host. MOTOROLA MC68SC302 USER’S MANUAL 3-1 ...
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... IRQIN4/RI is selected by properly programming the Port A control registers, a rising edge on the RI wakes up the SC302 from any of the low power modes. In PCMCIA mode, the PC_STSCHG pin does the same if selected and enabled. In ISA mode, an interrupt is generated to the PC after clock recovery. 3-2 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
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... SCC1 SCC2 SCC3 SMC1 SMC2 SCP The selected IRQOUT line will be asserted whenever the IPR register ANDed with the IMR register has a non-zero value. MOTOROLA Global Interrupt Mode Register (GIMR MD6[1] MD6[ PIT ...
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... PERIODIC TIMER PERIOD CALCULATION. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period 3-4 NOTE PIT RI - IRQIN6 IRQIN5 IRQIN4 IRQIN3 IRQIN2 IRQIN1 PITR count value+1 = -------------------------------------------------- - EXTAL -------------------------------------------------- - MC68SC302 USER’S MANUAL $816 MALL 1or512 4 MOTOROLA ...
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... The ISA Power Down Register (IPRDN) contains the PWRDN bit, used to reduce power consumption in the MC68SC302. PWRDN—Power down 0 = Wake-up mode 1 = Power-down mode The RI Event Indication Register (IOER) contains the RIEVT bit, used to detect a ring event and generate an interrupt. MOTOROLA ...
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... Ring event is detected Ring event is a status bit. Writing a one to it clears the bit, writing a zero has no effect. 3-6 RI Event Indication Register (IOER RSVD RSVD RSVD MC68SC302 USER’S MANUAL $804 RIEVT RSVD RSVD RSVD RSVD MOTOROLA ...
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... Main Controller (RISC Processor) • A Command Set Register • Serial Channels Physical Interface Including: — Motorola Interchip Digital Link (IDL) — General Circuit Interface (GCI), also known as IOM-2 — Pulse Code Modulation (PCM) Highway Interface — Nonmultiplexed Serial Interface (NMSI) • ...
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... FLG, but the host should still set FLG when setting RST. The CR, an 8-bit, memory-mapped, read-write register, is cleared by reset. Command Register (CR RST GCI OPCODE — 4-2 $861 CH. NUM. FLG MC68SC302 USER’S MANUAL MOTOROLA ...
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... Note that the execution of the STOP TRANSMIT or RESTART TRANSMIT commands may not affect the TXD pin until many clocks after the FLG bit is cleared by the CP, due to the transmit FIFO latency. MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-3 ...
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... The physical interface echo mode differs from the individual SCC echo mode in that it can operate on the entire multiplexed signal rather than just on a particular SCC channel (which may further have particular bits masked). Loopback mode causes the 4-4 MC68SC302 USER’S MANUAL MOTOROLA ...
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... IDL Interface The IDL interface is a full-duplex ISDN interface used to interconnect a physical layer device (such as the Motorola ISDN S/T transceiver MC145474 or MC145574 and ISDN U MC145472 or MC145572) to the SC302. Data on five channels (B1, B2 and M) is transferred in a 20-bit frame every 125 s, providing 160-kbps full-duplex bandwidth. The SC302 is an IDL slave device that is clocked by the IDL bus master (physical layer device) ...
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... The IDL bus has five channels: B1 64-kbps Bearer Channel B2 64-kbps Bearer Channel D 16-kbps Signaling Channel 8-kbps Maintenance Channel (not required by IDL and not sup- M ported by the SC302) 8-kbps Auxiliary Channel (not required by IDL and not supported A by the SC302) 4-6 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
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... The SC302 also supports another line for D-channel access control—the L1GRNT line. This signal is not part of the GCI interface definition and may be used in proprietary interfaces. When the L1GRNT line is not used, it should be pulled high. MOTOROLA IDL CHANNEL SERIAL CONTROLLERS D ...
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... The SC302 supports all five channels of the GCI channel 0. The following table shows where each channel can be routed. The two B channels can be concatenated and routed to the same SCC channel. GCI CHANNEL 0 SERIAL CONTROLLERS 4-8 NOTE D SCC1, SCC2, SCC3 B1 SCC1, SCC2, SCC3 B2 SCC1, SCC2, SCC3 M SMC1 C/I SMC2 MC68SC302 USER’S MANUAL MOTOROLA ...
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... L1CLK is always an input to the SC302 in PCM highway mode and is used as both a receive and transmit clock. Thus, data is transmitted and received simultaneously in PCM highway mode. (If receive data needs to be clocked into the SC302 at a different time or speed than MOTOROLA DEFINITION Receive Data ...
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... SCC1 desires to transmit over the PCM highway and will stay asserted until the entire frame is transmitted (regardless of how many time slots that takes). 4-10 PSYNC SELECTION Channel Selected 0 1 PCM Channel 1 Selected 1 0 PCM Channel 2 Selected 1 1 PCM Channel 3 Selected MC68SC302 USER’S MANUAL MOTOROLA ...
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... L1CLK PSYNC L1SYNC PCM CHANNEL 1 CONTAINS 8 BITS AND CAN BE ROUTED TO ANY SCC. NOTE: Whenever the syncs are active, data from that SCC is transmitted and received using L1CLK edges. Figure 4-3. PCM Channel Assignment on a T1/CEPT Line MOTOROLA PCM CHANNEL 3 CONTAINS 10 BITS AND CAN BE ROUTED TO ANY SCC ...
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... The channel automatically retransmits the received data on a bit-by-bit basis. The receiver operates normally, but the transmitter can only retransmit received data. In this mode, L1GRNT is ignored. 4- DRB MC68SC302 USER’S MANUAL $8B4 DRA MSC3 MSC2 MS1 MS0 MOTOROLA ...
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... MS0. NMSI pins are all available for other purposes SCC3 is not connected to a multiplexed serial interface but is either connected directly to the NMSI pins or not used. The choice of general-purpose I/O port pins versus SCC3 functions is made in the port A registers. MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-13 ...
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... SIMASK register Serial Interface Mask Register (SIMASK 4-14 NOTE MC68SC302 USER’S MANUAL $8B2 MOTOROLA ...
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... Thus, for a 20.48MHz system clock frequency, the serial clock must not exceed 8.19MHz. To provide modem serial output lines, the user must define I/O port pins as outputs in the port data direction register and write to the port A/B data register to cause the state of the pin to change. MOTOROLA NOTE MC68SC302 USER’S MANUAL Communications Processor (CP) 4-15 ...
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... DATA DATA REGISTER REGISTER SHIFTER SHIFTER Figure 4-4. SCC Block Diagram FSE RVD RTE FLG ENC DIAG1 MC68SC302 USER’S MANUAL TRANSMITTER CONTROL TXD $884, $894,$8A4 DIAG0 ENR ENT 0 MODE MOTOROLA ...
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... The receiver decodes NRZI, but a clock must be supplied. The transmitter encodes NRZI. During an idle condition, with the FLG bit cleared, the line will be forced to a high state. MOTOROLA NOTE MC68SC302 USER’S MANUAL Communications Processor (CP) ...
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... MODE—Channel Mode 0 = HDLC 1 = Totally Transparent 4.5.3 SCC Transmit Buffer Descriptors Data associated with each SCC channel is stored in buffers, which can be located anywhere inside the internal RAM. Each buffer is referenced by a BD, which also may be located anywhere in internal RAM. 4-18 MC68SC302 USER’S MANUAL MOTOROLA ...
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... Each BD is followed by its buffer, and the next BD is written right after that when opened, so there is no wasted space when buffers are closed earlier then expected, or when buffers are not used. 15 STATUS and CONTROL MOTOROLA DATA LENGTH DATA BUFFER POINTER Figure 4-5. Transmit BD DATA LENGTH Figure 4-7. Receive BD MC68SC302 USER’ ...
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... The host can read data only from buffers that were closed, i.e., with E=0. In HDLC mode an interrupt can be generated after each Frame Reception (RXF in SCCE). In transparent mode an interrupt is generated after each buffer reception. 4-20 Tx Buffer Descriptors Frame Status Data Length Data Pointer MC68SC302 USER’S MANUAL MOTOROLA ...
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... A BD always starts at an even address buffer length is odd, the byte after the last buffer byte is “garbage” and the next BD starts at the next even address. The host should consider this when calculating the next BD address. MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) ...
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... Communications Processor (CP) Programmable Base Figure 4-8. Rx Channel Memory Chunk 4-22 Data Length BD Status + DATA AREA Data Length BD Status DATA AREA BD Status Data Length DATA AREA MC68SC302 USER’S MANUAL MOTOROLA ...
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... CPU FIRST NOT HANDLED BD (RNH). The address of the first BD which is not handled by CPU in its interrupt service routine. 4.5.5.5 RX TIME-OUT(RTO). If the actual number of octets received exceeds this number and there is a valid data in the Rx chunk, an interrupt can be generated. MOTOROLA Table 4-3. SCC Parameter RAM Width Word ...
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... TBASE entry. Although TBPTR need never be written by the user in most applications (except after reset), it may be modified by the user when the transmitter is disabled, or when the user is sure that no transmit buffer is currently in use (e.g., after STOP TRANSMIT command is issued, and the frame completes its transmission). 4-24 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
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... SCC Mask Register (SCCM) This 8-bit read-write register allows enabling or disabling interrupt generation by the CP for specific events in each SCC channel. An interrupt will only be generated if the SCC interrupts for this channel are enabled in the IMR in the interrupt controller. MOTOROLA Rx Channel Memory Chunk DATA AREA ...
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... The SCC should be disabled and then re-enabled if any change is made to the SCC's parallel I/O or serial channels physical interface configuration. The SCC does not need to 4-26 SCC Status Register RESERVED MC68SC302 USER’S MANUAL $8xD – GRANT MOTOROLA ...
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... When the MODE bit of an SCC mode register (SCM) selects HDLC mode, then that SCC functions as an HDLC controller. The HDLC controller handles the basic functions of the HDLC/SDLC protocol on either the D channel channel, or from a multiplexed serial interface (IDL or GCI (IOM-2)). When the HDLC controller is used to support the MOTOROLA INFORMATION CONTROL (OPTIONAL) ...
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... Following the transmission of the closing flag, the HDLC controller writes the frame status bits into the BD and clears the ready bit. When the end of the current BD has been reached, and the last bit is not set (working in multibuffer mode), only the ready bit is cleared. In either 4-28 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
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... HDLC MEMORY MAP. When configured to operate in HDLC mode, the SC302 overlays the structure shown in Table 4-4 onto the protocol-specific area of that SCC parameter RAM. Refer to Table 4-3 for the placement of the SCC parameter RAM areas and the other protocol specific parameter RAM values. MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-29 ...
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... Constant ($XXXX 16-Bit CRC, $20E3 32-Bit CRC) Word Temp Transmit CRC Low Word Temp Transmit CRC High Word User-Defined Frame Address Mask Word User-Defined Frame Address Word User-Defined Frame Address Word User-Defined Frame Address Word User-Defined Frame Address MC68SC302 USER’S MANUAL DESCRIPTION MOTOROLA ...
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... RESTART TRANSMIT command. The transmit FIFO size is four words. 2. GRANT Lost (Collision) During Frame Transmission. When this error occurs and the channel is not programmed to control this line with software, the channel terminates buffer transmission, closes the buffer, sets the Collision(COL) bit in the BD, and gen- MOTOROLA NOTE FLAG ETC. ...
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... report information about the received data for each buffer. The shown in Figure 4-11 Figure 4-11. HDLC Receive Buffer Descriptor 4- -— MC68SC302 USER’S MANUAL LSB • • • 0 LEADING ZEROS NOT VALID DATA DATA LENGTH MOTOROLA ...
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... It is written by the CP once as the BD is closed. 4.5.10.9 HDLC TRANSMIT BUFFER DESCRIPTOR (TXBD) . Data is presented to the HDLC controller for transmission on an SCC channel by arranging it in buffers referenced by the channel's TxBD table. The HDLC controller confirms transmission (or indicates error MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-33 ...
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... CRC after the data Transmit the CRC sequence after the last data byte. UN—Underrun The HDLC controller encountered a transmitter underrun condition while transmitting the associated data buffer. 4- COL TX BUFFER POINTER MC68SC302 USER’S MANUAL DATA LENGTH MOTOROLA ...
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... A complete frame has been received on the HDLC channel. This bit is set no sooner than two receive clocks after receipt of the last bit of the closing flag. BSY—Busy Condition A frame was received and discarded due to lack of space in the receive chunk. MOTOROLA SCCE1 AT ADDRESS $889 ...
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... BD in the transmit channel's BD table approximately every 16 transmit clocks. When there is a buffer to transmit, the transparent controller will fetch the 4- SCCM1 AT ADDRESS $88B BSY TXB RTH/TO SCCM2 AT ADDRESS $89B SCCM3 AT ADDRESS $8AB MC68SC302 USER’S MANUAL MOTOROLA ...
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... For example, in NMSI mode, the first word of data will not be moved to the receive buffer until after the sixteenth receive clock occurs. Once synchronization is achieved for the receiver, the reception process continues unabated until a busy condition occurs or a receive overrun occurs. The busy condition error MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-37 ...
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... NAME WIDTH RES WORD RES WORD RES WORD RES WORD RES WORD RES WORD ZERO WORD RES WORD RES WORD RES WORD RES WORD MC68SC302 USER’S MANUAL DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MOTOROLA ...
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... TxBD last (L) bit set. Once synchronization is achieved for the receiver, it will remain in effect until an error occurs or the ENTER HUNT MODE command is given. 4.5.11.6 TRANSPARENT ERROR-HANDLING PROCEDURE. The transparent controller reports message reception and transmission error conditions using the channel BDs and the transparent event register. MOTOROLA MC68SC302 USER’S MANUAL Communications Processor (CP) 4-39 ...
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... The data buffer associated with this BD is empty. This bit signifies that the BD and its associated buffer are available to the CP. The host should not write to any fields 4- -— OV -— MC68SC302 USER’S MANUAL DATA LENGTH MOTOROLA ...
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... When this buffer is serviced by the CP, the TX or TXE bit in the transparent event register will be set, which can cause an interrupt. L—Last in Message 0 = The last byte in the buffer is not the last byte in the transmitted block. Data from the next transmit buffer (if ready) will be transmitted immediately following the last byte of this buffer. MOTOROLA ...
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... All unmasked bits must be cleared before the CP will negate the internal interrupt request signal. This register is cleared at reset. Transparent Event Register GRANT -— -— TXE 4- SCCE1 AT ADDRESS $889 BSY TX RTH SCCE2 AT ADDRESS $899 SCCE3 AT ADDRESS $8A9 MC68SC302 USER’S MANUAL MOTOROLA ...
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... SCC2/3 CODEC INTERFACE. SCC2 and SCC3 can be configured to interface to some popular CODECs (like the MC145554), as determined by the PACNT and SCON registers. The SC302 can generate the MCLK clock, needed for the CODEC sampling logic, MOTOROLA SCCM1 AT ADDRESS $88B ...
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... TXD MCLK SCLK FSYN Figure 4-15. Codec Interface Data Word Data Word Figure 4-16. FSYN Timing CD9 CD8 CD7 CD6 CD5 CD4 MC68SC302 USER’S MANUAL PA[4] SC302 PA[5] PA[6] PA[7] PA[ CD3 CD2 CD1 CD0 MOTOROLA $892 0 DIV4 0 ...
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... This column is valid only if the corresponding PACNT bit is set. ** The BRG is selected only if the corresponding MSCx bit In the SIMODE register is set. MOTOROLA NOTE *PA(6) PIN *PA(7) PIN *PA(8] PIN 0 BRG (O) BRG (O) 1 CLKRx (I) SDS1 (O) 0 BRG (O) CLKTx (I) 1 CLKRx (I) ...
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... The divide-by-4 option is useful in generating very slow baud rates. 4-46 DIV4 CD[10:0] BIT BITS PRESCALER 11 BIT DIVIDE BY 4 COUNTER CLKRX/SCLK PA[ RCS BIT MUX MUX CODS MUX MUX BIT TO SCC2/3 TO SCC2/3 TX CLOCK RX CLOCK NOTE MC68SC302 USER’S MANUAL CLKTX/MCLK PA[6] 1 FSYN PA[8] CODEC, 16 CLOCKS GENERATOR 1 MOTOROLA ...
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... The SCP allows the SC302 to exchange status and control information with a variety of serial devices, using a subset of the Motorola Serial Peripheral Interface (SPI). The SCP is compatible with SPI slave devices. These devices include industry-standard CODECs as well as other microcontrollers and peripherals. ...
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... When set, the SCPCLK begins toggling at the beginning of data transfer. When cleared, the SCPCLK begins toggling at the middle of the data transfer. 4- PM1 PM0 MC68SC302 USER’S MANUAL $8B0 SMD 0 LOOP EN2 EN1 MOTOROLA ...
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... Table 5-1 for ISA or Table 6-2 for PCMCIA.). Data loading from the serial EEPROM is not being done through the buffer descriptor but through the host bus interface. 4-49 SCP Transfer Format With SCP Transfer Format With MC68SC302 USER’S MANUAL LSB LSB X LSB LSB MOTOROLA ...
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... PNP EEPROM access. The SCP can also be used to program the PNP EEPROM using normal SCP accesses. 4.6.3.2.1 16- Bit Address EEPROM. In 16-bit address EEPROMs, a 1-byte read OP-Code (011 bin) precedes the 16 address bits. Data from the EEPROM appears on the byte following the address. 4- MC68SC302 USER’S MANUAL $74E 0 DATA MOTOROLA ...
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... MC68SC302 USER’S MANUAL data out data out MOTOROLA ...
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... GCI interface. The SMC ports are used only when the physical serial interface is configured for GCI mode. 4.7.1.1 USING GCI WITH THE SMCS. In this mode, SMC1 controls the GCI monitor channel. 4-52 7 lsb address NOTE MC68SC302 USER’S MANUAL data out MOTOROLA ...
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... SMC controllers and the serial interface. — When SMC loopback mode is chosen, SMC transmitted data is routed to the SMC receiver. Transmitted data appears on the L1TXD pin, unless the SDIAG1–SDIAG0 4-53 MC68SC302 USER’S MANUAL MOTOROLA ...
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... All the structures detailed in the following paragraphs reside in the parameter RAM of the SC302. The SMC buffer descriptors allow the user to define one data byte PM0 MC68SC302 USER’S MANUAL $8B0 SMD 0 LOOP EN2 EN1 MOTOROLA ...
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... AB—Received A Bit This bit is valid only in GCI mode when the monitor channel is in transparent mode. EB—Received E Bit This bit is valid only in GCI mode when the monitor channel is in transparent mode. 4- — NOTE MC68SC302 USER’S MANUAL $73A 0 DATA MOTOROLA ...
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... The data field contains the data to be transmitted by SMC1. 4.7.4.3 SMC2 RECEIVE BUFFER DESCRIPTOR. In the GCI mode, SMC2 is used to control the C/I channel. (For buffer descriptor address, see Table 5-1 for ISA or Table 6-2 for PCMCIA.) 4- — MC68SC302 USER’S MANUAL $73C 0 DATA MOTOROLA ...
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... Each of the two interrupt requests from each SMC is enabled when its respective SMC channel is enabled in the SPMODE register. Interrupt requests from SMC1 and SMC2 can be masked in the interrupt mask register. See Interrupt Controller for more details. 4- NOTE 6 5 MC68SC302 USER’S MANUAL $73E C $740 C MOTOROLA ...
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... Communications Processor (CP) 4.8 REVISION NUMBER The revision number of the part can be read at $73A. This is shared with the SMC1 RxBd, so the revision number is only valid after reset and before the SMC is used. 4-58 MC68SC302 USER’S MANUAL MOTOROLA ...
Page 91
... The DPR is further partitioned to a system RAM region and a parameter RAM region. These regions are shown in Figure 5-1. System RAM size is 1280 decimal bytes ($500 bytes). The Rx FIFO buffers and RxBDs, the TxBD table and Tx data buffers, are all contained in this portion of the DPR. MOTOROLA MC68SC302 USER’S MANUAL 5-1 ...
Page 92
... EEPROM device. This entry is loaded immediately following hard system reset to the Implementation Specific Information (ISI) register in the HCR. See ISA PNP Interface definition for details. 5-2 CCMR DPR SYSTEM RAM PARAMETER RAM CCR INTERNAL REGISTERS NOTE MC68SC302 USER’S MANUAL 0 4FF 500 7FF 800 FFF MOTOROLA ...
Page 93
... CCMR location pointed to by ADPTR. A 16-bit data word is loaded into DPORT. This data can be read either as two bytes in 8-bit data mode word in 16-bit data mode (if the master is making 8-bit transfers, the SC302 must be configured as an 8-bit slave). MOTOROLA NOTE SET_READ_DATA ...
Page 94
... BOOT. This 12-bit register points to a 4kbyte space within ISA memory address space. Any location within the CCMR can be randomly accessed. The value loaded into the base address register is 4kb aligned. 5.3.3 CCMR Structure Byte addressing of the CCMR is little endian (Intel convention). 5-4 NOTE NOTE MC68SC302 USER’S MANUAL in the DPR region of MOTOROLA ...
Page 95
... For detailed description of page parameter contents either for HDLC or TRANSPARENT protocols, please refer to CP definition. 5.3.3.3 CCR REGISTER MAP. The CCR register map is described in Table 5-2. The term CCMR address refers to the offset from the beginning of the CCMR. MOTOROLA ...
Page 96
... Special Pin Function in 8-Bit Mode 00 4.24.2 Command Set 4.5.2 00 4.5.10.10 HDLC Event Register 00 4.5.10.11 HDLC Mask Register 4.5.5.9 Transmitter Buffer Descriptor 00 Pointer (TBPTR) 4.5.2 00 4.5.10.10 HDLC Event Register 00 4.5.10.11 HDLC Mask Register 4.5.5.9 Transmitter Buffer Descriptor 00 Pointer (TBPTR) 4.5.2 00 4.5.10.10 HDLC Event Register 00 4.5.10.11 HDLC Mask Register 4.5.5.9 Transmitter Buffer Descriptor 00 Pointer (TBPTR) 4.6.1 4.4.1 MOTOROLA ...
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... Reserved for future use. Must be programmed to 0 0x07 Implementation Specific Information 0x08 First byte of Standard Resource Data The first two bytes are used to define EEPROM type and enforce debug mode. MOTOROLA NAME MC68SC302 USER’S MANUAL ISA Plug and Play Interface REGISTER-DESTINATION - ...
Page 98
... Bit 2–bit 0—The length of I/O range length masking pattern for CS0. See definition of bit 2–bit 0 in the Implementation Specific Information (ISI) register. 5-8 2 Table 5-4. Specifying SE PROM 2 PROM 8-BIT ADDRESS SE 0x00 0(d)000011 0x00 0x00 0x00 NOTE MC68SC302 USER’S MANUAL 2 2 PROM ISA-93C46 SE PROM 0(d)000010 0xFF 0x00 0x00 0x80 MOTOROLA ...
Page 99
... Figure 5-5. ISA-PNP Resource Data Layout in a Byte Serial EEPROM Device 5.4.2 Reading Resource Data There are two registers dedicated to resource data reading: resource data and status, both active only in the configuration state. MOTOROLA NOTE One logical device is defined for this application. ...
Page 100
... Byte 6: base alignment in 1-byte blocks. The base alignment of the internal space must be greater than or equal to 4 bytes. Byte 7: range length. For internal space it must be programmed to 4 bytes. For CS0 it should be programmed to the length of the related I/O region. 5-10 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
Page 101
... Bytes 8-9: base alignment = 4kbyte-range length of the internal memory space. Bytes 10-11: 16 256-byte blocks (=4kbyte-range length of the internal memory space). The memory descriptor related to the CS0 (the second memory descriptor) is programmed in the same way. Its fields have to reflect the properties of the CS0 memory region. MOTOROLA 0 I/O base IO_ADDRESS ...
Page 102
... NULL memory-descriptor: range length is set to 0x0000. The software writes 0x00 to the related configuration registers (0x40- 41, 0x43-44, for example). NULL I/O-descriptor: I/O base address is set to 0x0000. The software writes 0x00 to the related configuration registers. 5-12 NOTE NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
Page 103
... Otherwise, the ISA- data bus is not driven. For more details, see 5.14 Isolation Protocol. Configuration Control Write only. The register is active in sleep, isolation and configuration states. MOTOROLA RDA[6] RDA[5] NOTE 0/1 ...
Page 104
... EPROM). If Wake[0] was issued when a card is in the isolation state, the software must wait 1+ ms before beginning the next 72 pairs of serial isolation read cycles. 5-14 NOTE WCSN[4] WCSN[3] NOTE NOTE MC68SC302 USER’S MANUAL Address Port Value: 0x03 WCSN[2] WCSN[1] WCSN[0] MOTOROLA ...
Page 105
... The register can be written if the isolation has successfully completed. Writing the register causes a transition to the configuration state. The CSN can be reassigned in the configu- ration state. RESET_DRV (ISA-bus signal) and Reset CSN command reset CSN. A CSN value of 0x00 corresponds to an uninitialized CSN. MOTOROLA RD[4] ...
Page 106
... For 8.33 MHz ISA, for frequencies less than 15MHz, I/O space ICHRDY must be set 5- NOTE MC68SC302 USER’S MANUAL Address Port Value: 0x07 Address Port Value: 0x08-0x1F Address Port Value: 0x20 ICHRDY ECHRDY MOTOROLA ...
Page 107
... Low power mode is disabled. Internal clocks are not disabled following PwrDwn setting. ISI (Card Level Vendor Defined I_M/I CS_M/I LOADED FROM 0X11 IN BYTE SERIAL DEVICE Read/write Implementation Specific Information register. The register is active in the configuration state. MOTOROLA PMOD0 CDIV0 ...
Page 108
... A bit set in the range length mask indicates that the corresponding bit in the I/O address is used in the CS0’s address comparator. The register is loaded at reset (or reset command) from the corresponding fields of 0x07 of a byte serial device. 5-18 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
Page 109
... If the device is inactive and CHECK_EN = 1, reads of the logical device’s assigned I/O range return 0xAA. Logical Device Control Reserved The registers are unimplemented read access return 0x00. Logical Device Vendor Defined The registers are unimplemented read access return 0x00. MOTOROLA ...
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... BAR[12 NOTE MC68SC302 USER’S MANUAL Address Port Value: 0x40 BAR[18] BAR[17] BAR[16 Address Port Value: 0x41 Address Port Value: 0x42 DATA_SZ DEC MOTOROLA ...
Page 111
... Filler (filler 0) Unimplemented. On reads return 0. CSBARH-CSBARL (CS0 Memory Base[23–8], Descriptor 1) Address Port Value: 0x48- CSBAR[23] CSBAR[22] CSBAR[21 CSBAR[15] CSBAR[14] CSBAR[13 Read/write The registers are active in the configuration state. MOTOROLA RL[12] RL[11]= NOTE ...
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... Unimplemented. On reads return 0. 5- RL[20] RL[19 RL[12] RL[11 NOTE MC68SC302 USER’S MANUAL Address Port Value: 0x4A DATA_SZ DEC Address Port Values: 0x4B- RL[18] RL[17] RL[16 RL[10] RL[9] RL[ Address Port Values: 0x4D-4F MOTOROLA ...
Page 113
... The registers are active in the configuration state only. CS_BASE15–CS_BASE0—CS0 I/O base address bits15–0. If the memory configuration is chosen for a region, all the related I/O configuration registers are read only. The returned value is 0. I/0 Port Configuration (Descriptors 5-7) Unimplemented. On read return 0. MOTOROLA Address Port Values: 0x50-54, 0x58- I_BASE[12] ...
Page 114
... MC68SC302 USER’S MANUAL Address Port Value: 0x70 IRQL[2] IRQL[1] IRQL[ Address Port Value: 0x71 LVL Address Port Values: 0x72-73 Address Port Values: 0x74-75 Address Port Values: 0x76-A8 Address Port Values: 0xA9-0xFF MOTOROLA ...
Page 115
... CSN register in the isolation state) the ISA-data bus remains in a high impedance state. Write accesses are ignored. Write accesses to read-only registers are ignored (and read accesses to write-only registers) are ignored as well. MOTOROLA MC68SC302 USER’S MANUAL ISA Plug and Play Interface 5-25 ...
Page 116
... Bits[2:0] - Encoded Range Length Mask. See ISI register definition for details. Unimplemented. On reads return 0. MC68SC302 USER’S MANUAL ACTIVE IN THE FOLLOWING STATES Isolation, Configuration Isolation In any state, except Wait for Key. Sleep, Isolation, Configuration Configuration Configuration Con- End of Isolation, figuration Configuration Configuration Configuration Configuration Configuration Configuration MOTOROLA ...
Page 117
... Logical Device Con- 0x32-0x37 trol Reserved Logical Device Con- 0x38-0x3F trol Vendor Defined MOTOROLA DESCRIPTION The bits[7:1] are reserved and return read access. Bit[0], if set, activates the chip and it re- sponds to the ISA bus cycles. If reset, the chip is inactive. The register is read/write. ...
Page 118
... Memory base, control and length descriptor 2 (un- implemented) Reserved (unimplemented). On reads return 0. Memory base, control and length descriptor 3 (un- implemented). On reads return 0. Reserved (unimplemented). On reads return 0. MC68SC302 USER’S MANUAL ACTIVE IN THE FOLLOWING STATES Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration MOTOROLA ...
Page 119
... Table 5-11. 32-Bit Memory Space Configuration Summary ADDRESS NAME PORT VALUE 32-bit memory configuration 0x76-A8 MOTOROLA DESCRIPTION Base address[15:8] for internal I/O space. figuration option is chosen for the Internal Space, the registers located at 0x60-61 are read only and return 0 on reads. Base address[7:0] for internal I/O space CS0 base address ...
Page 120
... RSVD RSVD PWRDN RIEVT RSVD RSVD RSVD ET5 ET4 ET3 ET2 MOTOROLA $800 0 RSVD 0 $802 0 0 $804 0 RSVD 0 $812 0 ET1 0 $814 ...
Page 121
... NOF3 NOF2 NOF1 NOF0 C32 SCC1 Event Register (SCCE1 SCE7 SCE6 SCE5 SCE4 SCE3 MOTOROLA PIT RI - IRQI6 IRQI5 IRQI4 IRQI3 IRQI2 IRQIN1 MALL PA10 PA9 PA8 ...
Page 122
... ENR ENT SCM4 SCM3 SCM2 SCM1 – ENR ENT MOTOROLA $88B 0 SCM0 0 $88D 0 GRANT 0 $892 0 DIV4 0 $894 0 MODE 0 $89B 0 SCM0 0 $89D 0 GRANT 0 $8A4 0 MODE 0 ...
Page 123
... Wake (CSN) Address Port Value: $ WCSN WCSN WCSN WCSN WCSN [7] [6] [5] [4] [ Write only MOTOROLA SCC3 Mask Register (SCCM3 SCM7 SCM6 SCM5 SCC3 Status Register (SCCS3 RESERVED PM0 ...
Page 124
... X X Read/write LPEN MC68SC302 USER’S MANUAL Address Port Value: $ RD[4] RD[3] RD[2] RD[1] RD[ Address Port Value: $ Address Port Value: $08-0x1F Address Port Value: $ ICHRDY ECHRDY MOTOROLA ...
Page 125
... IBARL (Memory Base Address[15:8], Descriptor 0) Address Port Value: $ BAR[15] BAR[14] BAR[13] BAR[12 Read/write MOTOROLA SI (Card Level Vendor Defined I_M/I CS_M/I I_DW CS_DW * Read/write *Bit 6 reset value is loaded from 0x11 in byte serial device Active ...
Page 126
... Address Port Values: $45- CSBA CSBA CSBA CSBA CSBA R[13] R[12] R[11] R[10] R[ Address Port Value: $ DATA_SZ DEC Address Port Values: $4B- Address Port Values: $55-57 MOTOROLA RL[8 CSBA R( ...
Page 127
... The connection between the ISA-PNP hardware and ISA-bus is shown in Figure 5-7. The decoder detects ISA-bus accesses to the ISA-PNP hardware. The LFSR block protects the ISA-PNP configuration data from accidental damage. To enable access to the ISA-PNP hardware, software should first perform a predefined series of 32 write cycles to the address port (key transmission). MOTOROLA ...
Page 128
... OUTPUT ENABLE WRITE_DATA PORT ADDRESS REGISTER LFSR KEY ADDRESS PORT 6A, B5, DA, ED, F6, FB,7D, BE, DF, 6F, 37, 1B, 0D, 86, C3, 61, B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74, 3A, 9D, CE, E7, 73, 39 MC68SC302 USER’S MANUAL CARD CONTROL LOGICAL DEVICE CONTROL LOGICAL DEVICE CONFIGURATION SELECT ADDRESS PORT MOTOROLA ...
Page 129
... READ_DATA port and the values generated by the HOST’s checksum 1 generator 1. It should be noted (by software designer) that the check-sum bits are valid only during the serial isolation and are not valid if the resource data is accessed in the configuration state MOTOROLA Vendor ...
Page 130
... Wake[0] command: before the first read from Serial Isolation register. 1) After RESET_DRV - before the first access to ISA-PNP ports. 2) After Reset command was issued - before the first access to ISA-PNP ports. 1) Between subsequent pairs of read cycles from the Serial Isolation Register. MC68SC302 USER’S MANUAL MOTOROLA ...
Page 131
... The HOST must delay 2 +ms prior to accessing ISA-PNP ports after RESET_DRV or Reset command is issued. The initiation key sequence should be issued to activate the ISA-PNP interface. Read access to the ISA-PNP hardware does not impact the functionality of the card. MOTOROLA Isolation State Host: Read from the DATA port Host: read from Serial Isolation Reg ...
Page 132
... Wait for Key state, respond to the command. The resource data is accessed through the SCP interface, therefore on every access to the Resource Data bit SCP_BS in the BUSCNT register is asserted. An access to the SCP is not allowed if the SCP_BS bit is asserted. 5-42 NOTE MC68SC302 USER’S MANUAL MOTOROLA ...
Page 133
... Figure 6-1) is enabled. In the parallel PROM configuration (shown in Figure 6-1), the card information structure (CIS) information resides in a PROM which is connected to the PCMCIA bus and is selected by a chip select output, PC_CISCS. This option allows larger CIS memory spaces to be implemented without penalizing MOTOROLA MC68SC302 USER’S MANUAL 6-1 ...
Page 134
... Dual Ported Ram. CIS ROM PC_CISCS COMMON MEMORY Figure 6-1. Parallel EPROM Configuration CIS ROM SCP Figure 6-2. Serial EEPROM Configuration 6-2 D[0:7] ADDRESS DATA[15:0] SC302 PCMCIA CONFIG REGISTERS ADDRESS DATA[15:0] SC302 PCMCIA COMMON CONFIG MEMORY REGISTERS MC68SC302 USER’S MANUAL PCMCIA BUS PCMCIA BUS MOTOROLA ...
Page 135
... Table 6-2 and Table 6-3. For example, referring to Table 6-3, the Periodic Interrupt Timer Register (PITR) $802 in attribute memory space.The data bus is driven for any attribute memory access in the interval $0, $FFF. MOTOROLA n this mode would be located at i MC68SC302 USER’S MANUAL ...
Page 136
... A25 must be one, so our host driver will always write to common memory address $2000000+IMBAR to access address zero of the CCMR. 6-4 Note ATTRIBUTE MEMORY SPACE DPR CIS SYSTEM RAM PARAMETER RAM CCR INTERNAL REGISTERS CCMR CIS EEPROM Mode MC68SC302 USER’S MANUAL 000 4FF 500 7FF 800 FFF MOTOROLA ...
Page 137
... A25 high ($2000000). The shaded areas show asynchronous FCR’s as specified by the PC Card 95 standard. Access to the FCR registers is allowed during STOP low power mode. The unshaded registers are 68SC302 specific registers and are not asynchronous - the system clock must be running to access them. MOTOROLA COMMON MEMORY SPACE DPR SYSTEM ...
Page 138
... COR CSR PRR SCR IOER BUSCNT CLKCNT ISI ACTIVE IBARL IBARH IMCNT IMRNGL IMRNGH CSBARL CSBARH CSCNT CSRNGL CSRNGH CIS* SYSTEM RAM 4FF 4FE 501 500 PARAMETER RAM 7FE 7FF Figure 6-5. DPR Addressing MC68SC302 USER’S MANUAL MOTOROLA ...
Page 139
... For detailed description of page parameter contents either for HDLC or transparent protocols, please refer to Section 4 Communications Processor (CP). 6.5.2 CCR Register Map The CCR register map is shown in Table 6-3. The CCMR address is the offset from the beginning of the CCMR MOTOROLA BLOCK SCC1 SCC1 PARAMETER RAM Reserved ...
Page 140
... HDLC Event Register 00 4.5.10.11 HDLC Mask Register 4.5.5.9 Transmitter Buffer Descrip- 00 tor Pointer (TBPTR) 0000 4.5.2 SCC Mode Register (SCM) 00 4.5.10.10 HDLC Event Register 00 4.5.10.11 HDLC Mask Register 4.5.5.9 Transmitter Buffer Descrip- 00 tor Pointer (TBPTR) 1500 4.6.1 SCP Programming Model FFFF 4.4.1 Serial Interface Mode Regis- 0000 ter (SIMODE) MOTOROLA ...
Page 141
... SIGCHG is high and the SC302 is configured as MEMORY+I/O device. SIGCHG—Signal change 0 = The STSCHG signal is always non-active (high The STSCHG signal represents the value of the CHANGED bit. This bit is set/reset by the host. If RINGEN=0 (Disabled), it determines if the value of the CHANGED bit is transferred to the STSCHG signal. MOTOROLA CONFIGURATION INDEX 5 ...
Page 142
... RSVD RSVD This register can be read or written by the host. 6-10 NOTE RSVD RSVD RIEVT RSVD MC68SC302 USER’S MANUAL Attribute address $2000004 RSVD RREADY RSVD Attribute address $2000006 Attribute address $2000008 RSVD RSVD RIENA MOTOROLA ...
Page 143
... X Read/write. ERMU—Enable RAM Ucode. This bit is written by the software and enables the RISC controller to run microcode loaded to the dual ported RAM. CLKCNT PMOD1 - - Read/write The register is active in the configuration state. MOTOROLA CHANGE RIENA SIGCHG ...
Page 144
... PC_CE2, and A0 are shown in Table 6-8 and Table 6-9. Active Read/write. 6- CS_DW CS_RL[ MC68SC302 USER’S MANUAL PCMCIA Address: 0x2000044 CS_RL[2] CS_RL[1] CS_RL[ Attribute address $2000008 ACTV MOTOROLA ...
Page 145
... Bits 7–0 of the BAR are always zero. IMCNT (Memory Control Read/write. Bits 7–2 — Reserved. On read return zero. The bits are read only. DATA_SZ—Data Size The corresponding memory is 16-bit (data width The memory is 8-bit. MOTOROLA BAR[20] BAR[19 BAR[12] 0 ...
Page 146
... NOTE CSBAR[20] CSBAR[19 CSBAR[12] CSBAR[11 MC68SC302 USER’S MANUAL Attribute address $2000088 RL[18]=RL[12] RL[17]=RL[12] RL[16]=RL[12 Attribute address $2000086 RL[10]=0 RL[9]=0 RL[8]= Attribute address $2000092- CSBAR[18] CSBAR[17] CSBAR[16 CSBAR[10] CSBAR[9] CSBAR8 MOTOROLA ...
Page 147
... Read/write The registers are active in the configuration state. RL23–RL8 — Range length of the corresponding memory space (corresponding to CS0). If the I/O configuration is chosen for a region, all the related memory configuration registers are read only. The returned value is 0. MOTOROLA ...
Page 148
... PC_D[15:8] PC_D[7:0] x xxx High-Z L xxx Even- Byte L xxx xxx L xxx Even-Byte L xxx xxx SELECTED REGISTER OR SPACE CIS Memory Read CIS Memory Write HCR Read HCR Write PC_D15- PC_D7-PC_D0 PC_D8 x High-Z High-Z H High-Z Even- Byte H High-Z Odd-Byte H Odd-Byte Even-Byte H Odd-Byte High-Z MOTOROLA ...
Page 149
... Following PwrDwn setting, the clock oscillator is enabled, but the 1 internal clocks are disabled. 1 Following PwrDwn setting, the clock oscillator is stopped. MC68SC302 USER’S MANUAL PC_D15- PC_WE PC_D7-PC_D0 PC_D8 x xxx xxx L xxx Even- Byte L xxx Odd-Byte Odd- L Even-Byte Byte Odd- L XXX Byte MOTOROLA ...
Page 150
... IO16 PCMCIA IO space is not supported in the SC302 INPACK PCMCIA IO space is not supported in the SC302 SPKR Carries binary audio signal DATA BITS [7:0] byte #0 $02 byte #1 CIS size (MSB) byte #2 CIS size (LSB) byte #3 and on CIS data MC68SC302 USER’S MANUAL DESCRIPTION MOTOROLA ...
Page 151
... PCMCIA Interface Table 6-13. 8-Bit Address Serial EEPROM Format (25xxx or 95xxx) 6-19 DATA BITS [7:0] byte #0 Reserved byte #1 $02 byte #2 CIS size (MSB) byte #3 CIS size (LSB) byte #4 and on CIS data MC68SC302 USER’S MANUAL MOTOROLA ...
Page 152
... PCMCIA Interface 6-20 MC68SC302 USER’S MANUAL MOTOROLA ...
Page 153
... I/O where the power dissipation on pins. I/O For and 20.48 MHz, 5.25 V, and TQFP A I/O package, the worst case value (5. 52.8 C/W) = 78.3C J MOTOROLA Symbol Value V – – – 150 stg Symbol Value 52 ...
Page 154
... Symbol MC68SC302 USER’S MANUAL C/W , and the values Symbol Typ Max 100 Min Max Unit V 2 –0 –0.3 0 MOTOROLA Unit ...
Page 155
... SCPTxD,SCPCLK, L1GRNT,L1RQ,CLKO (I =5.0 mA) L1TxD,TxD OL (I =7.0 mA) L1TxD,TxD OL (I =9.0 mA) PCMCIA mode: OL PC_D[0–15], IRQSEL,IRQO,PC_IREQ PC_STSCHG,PC_WAIT,PC_CISCS (I =24.0 mA) ISA mode: OL SD[0–15], IRQSEL,IRQO,IRQ3 IOCS16,IOCHRDY,MEMCS16 Output Drive CLKO Output Drive All Other Pins Power Common MOTOROLA CC V 0.8*V CIH V V CIL TSL V 2 ...
Page 156
... EXTAL t clk2 Figure 7-1. CLKOUT Timing Specifications 7-4 t clk3 t clk1 MC68SC302 USER’S MANUAL 15.36MHZ 20.48MHZ UNITS MIN MAX MIN MAX 65.1 48 – 31.5 33.5 23.5 25.5 ns 31.5 33.5 23.5 25 48.8 ns 13.5 40 – 63.5 66 65.5 66 130 130.5 97 70.5 76.5 ns Midpoint MOTOROLA ...
Page 157
... CLKOUT Figure 7-2. CLKOUT Timing for CDIV 1-0=00 in CLKCNT EXTAL t clk8 CLKOUT Figure 7-3. CLKOUT Timing for CDIV 1-0=10 in CLKCNT EXTAL t clk4 t clk5 CLKOUT Figure 7-4. CLKOUT Timing for CDIV 1-0=01 in CLKCNT MOTOROLA t clk5 t clk6 t clk7 t clk9 t clk11 t clk6 MC68SC302 USER’S MANUAL Electrical Characteristics t clk10 ...
Page 158
... (input) RESET (input) IOW (input) IOR (input) Figure 7-5. ISA Reset Timing Specifications 7-6 15.36MHZ MIN MAX irst6 t irst1 t irst3 t irst5 MC68SC302 USER’S MANUAL 20.48MHZ UNITS MIN MAX irst2 t irst4 MOTOROLA ...
Page 159
... IOW to Data Valid (Special case: Coupled Accesses) pnpr5 t Data Hold time from IOR rising edge pnpr6 t IOR active to data out valid pnpr8 t IOW to IOR delay for non Coupled Accesses pnpr9 MOTOROLA CHARACTERISTICS MC68SC302 USER’S MANUAL Electrical Characteristics 15.36MHZ 20.48MHZ UNITS MIN MAX MIN MAX ...
Page 160
... MC68SC302 USER’S MANUAL t pnpr2 t ir2 data-port t pnpr1 t ir1 t pnpr3 t ir3 t t ir15 ir15 t ir7 t pnpw5 pnpr6 t iw5 ir6 output pnpr8 ir8 MOTOROLA ...
Page 161
... SA[15:0],AEN,SBHE (input) IOW (input) IOR (input) NMSICS (output) IOCS16 (output) SD[15:0] Figure 7-7. IO Space Read Access without Wait States (PnP and Internal Space) - the Special Case of Coupled Accesses MOTOROLA write address port address-port t pnpr1 t ir1 t pnpr4 t ir4 t t iw11 iw11 t iw6 t pnpr5 t ir5 input MC68SC302 USER’ ...
Page 162
... NMSICS (output) IOCS16 (output) SD[15:0] Figure 7-8. IO Space Read Access without Wait States (Internal Space) 7-10 t ir2 data-port t t ir1 t ir3 t t ir15 ir15 t ir9 t ir7 t ir6 output MC68SC302 USER’S MANUAL t ir2 data-port ir1 t ir3 t ir15 t ir7 t t ir8 ir6 output MOTOROLA ...
Page 163
... SA[15:0],AEN,SBHE (input) IOR (input) NMSICS (output) IOCS16 (output) SD[15:0] Figure 7-9. IO Space Read Access without Wait States (Internal Space) - the Special Case of Coupled Read Accesses MOTOROLA t ir2 data-port t t ir1 t ir3 t t ir15 ir15 t ir4 t ir7 t ir6 output MC68SC302 USER’S MANUAL Electrical Characteristics ...
Page 164
... Electrical Characteristics SA[15:0],AEN,SBHE (input) IOR (input) NMSICS (output) IOCS16 (output) SD[15:0] (output) IOCHRDY (output) Figure 7-10. IO Space Read Access with Wait States 7-12 t ir1 t ir15 t ir7 valid t ir13 t t ir10 ir12 t ir11 MC68SC302 USER’S MANUAL t ir2 t ir14 t ir15 t ir6 MOTOROLA ...
Page 165
... IOW active to inactive pnpw3 t Data valid setup to IOW rising edge (Inactivation) pnpw4 t Data hold time from IOW rising edge (Inactivation) pnpw5 t IOW inactive time pnpw7 MOTOROLA CHARACTERISTICS MIN MC68SC302 USER’S MANUAL Electrical Characteristics 15.36MHZ 20.48MHZ MIN ...
Page 166
... Electrical Characteristics SA[15:0],AEN,SBHE (input) IOW (input) NMSICS (output) IOCS16 (output) SD[15:0] (input) Figure 7-11. IO Space Write Access without Wait states (PnP 7-14 t pnpw1 t iw1 t pnpw3 t iw3 t iw11 t iw6 t pnpw4 t iw4 and Internal Space) MC68SC302 USER’S MANUAL t pnpw2 t iw2 t pnpw7 t iw7 t iw11 t pnpw5 t iw5 MOTOROLA ...
Page 167
... SA[15:0],AEN,SBHE (input) IOW (input) NMSICS (output) IOCS16 (output) SD[15:0] (input) IOCHRDY (output) Figure 7-12. IO Space Write Access with Wait States - Internal Space MOTOROLA t iw1 t iw11 t iw6 t t iw9 iw8 t iw10 MC68SC302 USER’S MANUAL Electrical Characteristics t iw2 t iw7 t iw11 t t iw4 iw5 7-15 ...
Page 168
... MC68SC302 USER’S MANUAL 20.48MHZ UNITS MAX MIN MAX 170 203 162 120 MOTOROLA ...
Page 169
... BALE (input) REF (input) LA23–LA17 (input) SA15–SA0, SBHE (input) MEM CS16 (output) MEMR (input) NMSICS (output) D15–D0 (output) Figure 7-13. Memory Space Read Access without Wait MOTOROLA cycle-length t mr2 t mr16 t mr14 t mr3 t mr1 t mr9 t mr5 t mr6 t mr7 t mr8 t mr22 ...
Page 170
... D15–D0 (output) IOCHRDY (output) Figure 7-14. Memory Space Read Access with Wait 7-18 cycle-length mr2 t mr3 mr1 t mr9 t mr5 t mr6 t mr7 t mr22 t mr21 VALID t mr4 t mr18 t mr19 States MC68SC302 USER’S MANUAL t mr13 t mr15 t mr17 t mr23 t mr22 t mr12 accessed resource t mr20 MOTOROLA ...
Page 171
... IOCHRDY inactive (Low) pulse width mw19 t MEMW active (Low) hold from IOCHRDY active (High) mw20 MEMW active or inactive to NMSICS active or inactive de- t mw21 lay MEMW inactive to active (Rising to falling edge delay) with t mw22 wait states MOTOROLA 15.36MHZ MIN 200 25 40 100 ...
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... MEMW (output) NMSICS (output) D15–D0 (input) Figure 7-15. Memory Space Write Access without Wait 7-20 cycle-length t mw2 t mw16 t mw14 t mw3 t mw1 t mw9 t mw5 t mw6 t mw7 t mw8 t mw4 t mw21 t mw10 VALID States MC68SC302 USER’S MANUAL t mw13 t mw15 t mw17 t mw11 t mw21 t mw12 MOTOROLA ...
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... BALE (input) REF (input) LA23–LA17 (input) SA15–SA0,SBHE (input) MEM CS16 (output) MEMW (output) NMSICS (output) D15–D0 (input) IOCHRDY (output) Figure 7-16. Memory Space Write Access with Wait MOTOROLA cycle-length t mw2 t mw16 t mw14 t mw3 t mw1 t mw9 t mw5 t mw6 t mw7 t mw4 ...
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... CISCS from OE delay pr12 t NMSICS from OE delay pr13 7-22 15.36MHZ MIN 200 160 MC68SC302 USER’S MANUAL 20.48MHZ UNITS MAX MIN MAX 150 200 120 150 MOTOROLA ...
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... A[25:0],REG (input) CE (input (input) NMSICS (output) PC_CISCS (output) WAIT (output) D[15:0] (output) Figure 7-17. PCMCIA Read Access with/without Wait MOTOROLA t pr1 t pr3 pr4 t pr13 t pr12 t t pr7 pr8 t pr5 States MC68SC302 USER’S MANUAL Electrical Characteristics t pr2 t pr6 t pr13 t pr12 t pr9 t pr11 ...
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... CHARACTERISTICS MC68SC302 USER’S MANUAL 15.36MHZ 20.48MHZ UNITS MIN MAX MIN MAX 200 150 135 100 160 200 120 150 MOTOROLA ...
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... A[25:0],REG (input) CE (input) OE (input) WE (input) NMSICS (output) PC_CISCS (output) WAIT (output) D[15:0] (input) Figure 7-18. PCMCIA Write Access with/without Wait States MOTOROLA t pw1 t pw2 t pw4 t pw5 t pw11 t pw15 t pw14 t pw7 t pw8 t pw12 data–input-established MC68SC302 USER’S MANUAL Electrical Characteristics t pw3 t pw6 t pw10 ...
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... PC_MODE (input) PC_E2E (input) OE, WE (input) Figure 7-19. PCMCIA Reset Timing Specifications 7-26 15.36MHZ MIN prst7 t prst1 t prst3 t prst2 t prst6 t prst5 t prst4 MC68SC302 USER’S MANUAL 20.48MHZ UNITS MAX MIN MAX - MOTOROLA ...
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... Scpclk Rise Time scp7 t Scpclk Fall Time scp8 t scp2 SCPCLK-(ci=0) (reset value) (output) SCPCLK–(ci=1) (output) t scp3 SCPRxD (input) SCPTxD "1" (output) Figure 7-20. SCP Timing (cp=0, Reset Value) MOTOROLA 15.36MHZ MIN MAX scp8 t scp2 t scp4 t scp7 MSB-IN ...
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... DATA Figure 7-21. SCP Timing (cp=1) 15.36MHZ MIN MC68SC302 USER’S MANUAL LSB-IN MSB-IN t scp5 "1" LSB-OUT MSB-OUT 20.48MHZ UNITS MAX MIN MAX 44 Clks 20 Clks Clks 22 Clks 20 Clks MOTOROLA ...
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... SCPCLK (output) E2EN (output) SCPEN3–1 (output) t e2p11 SCPTxD Address (output) MSB/0 SCPRxD (input) Figure 7-22. Serial EEPROM (SCP Type) Timing Specifications (with Initial Reset Value of spmode) MOTOROLA t e2p8 t t e2p2 e2p7 t e2p2 t e2p5 A7/ A15 MC68SC302 USER’S MANUAL Electrical Characteristics t e2p1 ...
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... SCPEN3–1 (output e2p11 e2p5 SCPTxD opcode opcode (output) SCPRxD (input) Figure 7-23. Serial EEPROM (93C46 TYPE) TIMING SPECIFICATIONS (With Initial Reset Value of spmode) 7-30 t e2p8 t t e2p2 e2p7 t e2p2 t e2p5 A6 A0 MC68SC302 USER’S MANUAL t e2p1 t e2p9 t t e2p3 e2p4 D7 D0 MOTOROLA ...
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... Rising Edge SDS1–SDS2 Inactive Delay from L1CLK t idl17 Falling Edge NOTES: 1. The ratio EXTAL/L1CLK must be greater then 2.5/1. 2. High impedance is measured at the 30% and 70 through 10k in parallel with 130 pF. 3. Where P=1/EXTAL Thus, for a 20.48-MHz EXTAL rate, P=48.8 ns. MOTOROLA 15.36MHZ MIN MAX - p+10 - ...
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L1SYNC (input) t idl5 L1CLK (input idl8 L1TxD B17 B16 B15 (output) t idl11 L1RxD B17 B16 B15 (input) t idl10 SDS1–SDS2 (output) t idl13 L1RQ (output) t idl14 L1GRNT (input) t idl12 t idl7 ...
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... The ratio CLKO/L1CLK must be greater than 2.5/1. 2. Condition CL=150 pF L1TxD becomes valid after the L1CLK rising edge or L1SYNC, whichever is later. 3. SDS1–SDS2 becomes valid after the L1CLK rising edge or L1SYNC, whichever is later. 4. Where P=1/CLKO. Thus, for a 20.48 MHz CLKO rate, P=48.8 ns. MOTOROLA 15.36MHZ MIN MAX - ...
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... L1CLK (input) t gci4 L1SYNC (input) t gci7 t gci12 L1TxD (output) t gci6 t gci8 L1RxD (input) t gci11 SDS1–SDS2 (output) GCIDCL (output) Figure 7-25. GCI Timing Specifications 7- gci3n gci2n t t gci3m gci2m t gci5 t gci10 t gci9 t gci14 MC68SC302 USER’S MANUAL t gci1n t gci1m t gci13 MOTOROLA ...
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... PCM highway. 3. Specification valid for both sync methods. 4. Where p=1/CLKO. Thus, for a 20.48-MHz CLKO rate, p=48.8 ns L1SYNC/PSYNC is guaranteed to make a smooth low to high transition (no spikes) while L1CLK is high, setup time can be measured to L1CLK falling edge. MOTOROLA Table 7-17. PCM Timing 15.36MHZ MIN MAX ...
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... MC68SC302 USER’S MANUAL n-1 n pcm1 t pcm3 t pcm2 n pcm1 pcm4 MOTOROLA t pcm7 t pcm7 ...
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... The input clock to the baud rate generator may be either an internal clock or TIN1, and may be faster as EXTAL. However, the output of the baud rate generator must provide a CLKO/CLKTX and CLKO/CLKRX ratio greater than or equal to 3/1. 2.Where p=1/CLKO. Thus, for a 20.48-MHz CLKO rate, p=48.8 ns. MOTOROLA 15.36MHZ MIN MAX ...
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... CLKRx t nm-int7 t nm-ext7 t nm-int6 t nm-ext6 RxD (input) Figure 7-28. NMSI Timing Specifications 7- nm-int3 nm-int4 t t nm-ext3 nm-ext4 t nm-int5 t nm-ext5 t t nm-int3 nm-int4 t t nm-ext3 nm-ext4 MC68SC302 USER’S MANUAL t nm-int1 t nm-ext1 t nm-int2 t nm-ext2 t nm-int1 t nm-ext1 t nm-int2 t nm-ext2 MOTOROLA ...
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... MEMR MEMW VCC GND SD8 SD9 SD10 SD11 GND GND VCC SD12 SD13 SD14 SD15 LA23 LA22 LA21 25 26 MOTOROLA MC68SC302PU Top View MC68SC302 USER’S MANUAL 76 IRQ15 75 IOCHRDY IRQ11 IRQ10 IRQ9 GND GND VCC IRQ12 MEMCS16 IOCS16 IRQ3 VCC GND ...
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... BSC 0.630 BSC V1 8.00 BSC 0.315 BSC W 0.20 REF 0.008 REF Z 1.00 REF 0.039 REF BASE METAL PLATING –X– 0.08 (0.003 SECTION AB–AB ROTATED 90 CLOCKWISE DATE 07/14/94 MOTOROLA N S ...
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... ORDERING INFORMATION PACKAGE TYPE Surface Mount TQFP 100-Pin (PU Suffix) MOTOROLA Mechanical Data and Ordering Information FREQUENCY TEMPERATURE (MHZ 20.48 MC68SC302 USER’S MANUAL ORDER NUMBER MC68SC302PU20 8-3 ...
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... Mechanical Data and Ordering Information 8-4 MC68SC302 USER’S MANUAL MOTOROLA ...