UT52L1664MC-7 Utron Technology, Inc., UT52L1664MC-7 Datasheet
UT52L1664MC-7
Related parts for UT52L1664MC-7
UT52L1664MC-7 Summary of contents
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UTRON Rev. 1.2 REVISION HISTORY REVISION Rev.1.0 Revised 1. AC TIMING REQUIREMENTS Rev.1.1 2. Output Load Condition Rev.1.2 1. Add Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan ...
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UTRON Rev. 1.2 DESCRIPTION UT52L0464 is organized as 4-bank x 4,194,304- word x 4-bit Synchronous DRAM with LVTTL interface and UT52L0864 is organized as 4-bank x 2,097,152-word x 8-bit and organized as 4-bank x 1,048,576-word x 16-bit. All FEATURES ...
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UTRON Rev. 1.2 PIN CONFIGURATION(TOP VIEW) Vdd Vdd NC DQ0 VddQ VddQ NC NC DQ0 DQ1 VssQ VssQ DQ2 VddQ VddQ NC NC DQ1 DQ3 VssQ VssQ NC NC Vdd Vdd NC NC DQML /WE /WE ...
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UTRON Rev. 1.2 CLK：Master Clock CKE：Clock Enable /CS：Chip Select /RAS：Row Address Strobe /CAS：Column Address Strobe /WE：Write Enable DQ0-15：Data I/O UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5777882 FAX: ...
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UTRON Rev. 1.2 BLOCK DIAGRAM Memory Array 4096 X 512 X 8 Cell Array Bank #0 Mode Register Address Buffer A0-11 BA0,1 CLK Note：This figure shows the UT52L0864 The UT52L0464 configuration is 4096x1024x4 of cell array and DQ0-3 The ...
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UTRON Rev. 1.2 PIN FUNCTION CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0-11 Input BA0,1 Input DQ0-3(x4), DQ0-7(x8), Input/Output DQ0-15(x16) DQM(x4,x8), Input DQMU/L(x16) Vdd,Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ,VssQ ...
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UTRON Rev. 1.2 BASIC FUNCTIONS The UT52L0464,0864and 1664 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at ...
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UTRON Rev. 1.2 COMMAND TRUTH TABLE COMMAND MNEMONIC Deselect No Operation Row Address Entry & Bank Active Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE Current /CS /RAS /CAS /WE State IDLE ROW H ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE (continued) Current /CS /RAS /CAS /WE State READ ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE READ with H X AUTO PRECHARGE WRITE with H X ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE PRE CHARGING ROW H X ACTIVATING ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE WTITE H X RECOVERING REFRESHING ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE MODE H X REGISTER SETTING UTRON TECHNOLOGY INC. 1F, No. 11, R&D ...
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UTRON Rev. 1.2 FUNCTION TRUTH TABLE for CKE CKE CKE Current State n SELF REFRESH POWER DOWN ...
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UTRON Rev. 1.2 SIMPLIFIED STATE DIAGRAM MODE REGISTER SET SUSPEND CKEL WRITE SUSPEND CKEH WRITEA CKEL WRITEA WRITEA SUSPEND CKEH POWER POWER ON APPLIED UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. ...
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UTRON Rev. 1.2 POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and ...
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UTRON Rev. 1.2 CLK Read Command Y Address DQ CL=3 /CAS Latency BL=4 Initial Address ...
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UTRON Rev. 1.2 OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval ...
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UTRON Rev. 1.2 Multi Bank Interleaving READ (BL=4, CL=3) CLK ACT Command A0 A10 A11 Xa BA0 READ with Auto-Precharge (BL=4, CL=3) CLK ACT Command Xa A0-9 Xa A10 A11 Xa BA0 READ ...
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UTRON Rev. 1.2 WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the ...
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UTRON Rev. 1.2 BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK. CLK Command READ ...
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UTRON Rev. 1.2 [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent ...
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UTRON Rev. 1.2 [Read Interrupted by Burst Terminate] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 ...
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UTRON Rev. 1.2 [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. CLK Command Write Write Yi ...
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UTRON Rev. 1.2 [Write Interrupted by Precharge] Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by ...
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UTRON Rev. 1.2 [Write with Auto-Precharge Interrupted by Write or Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by ...
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UTRON Rev. 1.2 [Read with Auto-Precharge Interrupted by Read to another Bank] Burst Read with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by a command ...
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UTRON Rev. 1.2 AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells. The ...
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UTRON Rev. 1.2 SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated maintained as long as CKE is kept low. During the ...
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UTRON Rev. 1.2 CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend ...
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UTRON Rev. 1.2 DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM(U,L) masks input data word by word. DQM(U,L) to write mask latency is ...
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UTRON Rev. 1.2 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vdd Supply Voltage VddQ Supply Voltage for Output VI Input Voltage VO Output Voltage IO Output Current Pd Power Dissipation Topr Operating Temperature Tstg Storage Temperature RECOMMENDED OPERATING CONDITIONS (Ta=0-70℃,unless otherwise ...
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UTRON Rev. 1.2 AVERAGE SUPPLY CURRENT from Vdd (Ta=0-70℃,Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted) ITEM Symbol tRC=min,tCLK=min, Operating current Icc1 BL=1,IOL=0mA CKE=VIHmin Icc2N Precharge Standby tCLK=15ns current in Non- Power down mode Icc2NS CKE=VIHmin tCLK=VILmax(fixed) CKE=VILmax Precharge Standby Icc2P tCLK=15ns(Note) current in ...
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UTRON Rev. 1.2 AC TIMING REQUIREMENTS (Ta=0-70℃,Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted) Input Pulse Levels:0.4V-2.4V Input Timing Measurement Level:1.4V Symbol Parameter tCLK CLK cycle time tCH CLK High pulse width tCL CLK Low pulse width tT Transition time of CLK tIS Input ...
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UTRON Rev. 1.2 SWITCHING CHARACTERISTICS (Ta=0-70℃,Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted) Parameter Symbol tAC Access time from CLK tOH Output Hold time from CLK Delay time, output low-impedance tOLZ from CLk Delay time, output high-impedance tOHZ from CLK NOTE clock ...
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UTRON Rev. 1.2 Burst Write (single bank) @BL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE#0 UTRON TECHNOLOGY INC. 1F, ...
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UTRON Rev. 1.2 Burst Write (multi bank) @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ...
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UTRON Rev. 1.2 Burst Read (single bank) @BL=4 CL CLK /CS tRAS /RAS tRCD tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0,1 DQ ACT#0 READ#0 UTRON TECHNOLOGY INC. ...
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UTRON Rev. 1.2 Burst Read (multiple bank) @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0,1 DQ READA#0 ACT#0 ACT#1 UTRON TECHNOLOGY INC. ...
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UTRON Rev. 1.2 Write Interrupted by Write @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ...
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UTRON Rev. 1.2 Read Interrupted by Read @BL=4,CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0,1 DQ ACT#0 READ#0 ACT#1 UTRON TECHNOLOGY INC. 1F, ...
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UTRON Rev. 1.2 Write Interrupted by Read, Read Interrupted by Write @BL=4,CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9, BA0,1 DQ ACT#0 ...
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UTRON Rev. 1.2 Write/Read Terminated by Precharge @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0 ACT#0 WRITE#0 UTRON TECHNOLOGY INC. 1F, No. ...
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UTRON Rev. 1.2 Write/Read Terminated by Burst Terminate @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0 ACT#0 WRITE#0 UTRON TECHNOLOGY INC. 1F, ...
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UTRON Rev. 1.2 Single Write Burst Read @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM X Y A0-8 X A10 X A9, BA0 ACT#0 WRITE#0 UTRON TECHNOLOGY INC. 1F, No. ...
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UTRON Rev. 1.2 Power-Up Sequesce and Intialize CLK 200uS /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ NOP PRE ALL Power On UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based ...
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UTRON Rev. 1.2 Auto Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL PREA UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, ...
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UTRON Rev. 1.2 Self Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL Self Refresh Entry All banks must be idle before REFS is issued UTRON TECHNOLOGY INC. ...
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UTRON Rev. 1.2 CLK Suspension @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0 A10 A9, BA0 ACT#0 WRITE#0 UTRON TECHNOLOGY INC. 1F, No. 11, R&D ...
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UTRON Rev. 1.2 Power Down CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan ...
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UTRON Rev. 1.2 PACKAGE OUTLINE DIMENSION 54 pin 400mil TSOP II Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5777882 FAX: 886-3-5777919 UT52L1664/0864/0464 64M(X16-BITS / X8-BITS ...
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... Rev. 1.2 ORDERING INFORMATION PART NO. UT52L0464MC-6 UT52L0864MC-6 UT52L1664MC-6 UT52L0464MC-7 UT52L0864MC-7 UT52L1664MC-7 UT52L0464MC-7.5 UT52L0864MC-7.5 UT52L1664MC-7.5 UT52L0464MC-8 UT52L0864MC-8 UT52L1664MC-8 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5777882 FAX: 886-3-5777919 UT52L1664/0864/0464 64M(X16-BITS / X8-BITS / X4-BITS)SDRAM ACCESS TIME 6ns 7ns 7 ...
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UTRON Rev. 1.2 This Page Is Left Blank Intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5777882 FAX: 886-3-5777919 UT52L1664/0864/0464 64M(X16-BITS / X8-BITS / X4-BITS)SDRAM 53 P90006 ...