RC28F640P33T85 Numonyx/Intel, RC28F640P33T85 Datasheet
RC28F640P33T85
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RC28F640P33T85 Summary of contents
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Numonyx™ StrataFlash (P33) Product Features High performance: — initial access — 52MHz with zero wait states, 17ns clock-to- data output synchronous-burst read mode — asynchronous-page read mode — 4-, 8-, 16-, and continuous-word burst mode — ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal L ines and D isc laim er s OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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Numonyx™ StrataFlash Embedded Memory (P33) Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Virtual Chip Enable Description.............................................................................. 8 3.0 Package Information ............................................................................................... 10 3.1 56-Lead ...
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Programming Operations ....................................................................................57 11.3.1 Word Programming .................................................................................58 11.3.2 Buffered Programming ............................................................................58 11.3.3 Buffered Enhanced Factory Programming ...................................................59 11.3.4 Program Suspend ...................................................................................61 11.3.5 Program Resume ....................................................................................62 11.3.6 Program Protection .................................................................................62 11.4 Erase Operations ...............................................................................................62 11.4.1 Block Erase ............................................................................................62 11.4.2 Erase ...
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Numonyx™ StrataFlash Embedded Memory (P33) Revision History Date Revision Description April 2006 001 Initial release August 2006 002 Product release Update and provide general document clarifications Revise ICCR values for Page-Mode Read Added note for V Added TSOP Burst ...
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Introduction This document provides information about the Numonyx™ StrataFlash Memory (P33) device and describes its features, operation, and specifications. P33 is the latest generation of Numonyx™ StrataFlash 64-Mbit up through 512-Mbit densities, the P33 flash memory device brings reliable, ...
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Numonyx™ StrataFlash Embedded Memory (P33) 1.3 Conventions VCC : SR[4] : A[15: Bit : Byte : Word : Kbit : KByte : KWord : Mbit : MByte : MWord ...
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Functional Overview This section provides an overview of the features and capabilities of the Numonyx™ ® StrataFlash Embedded Memory (P33) device. The Kearny Family Flash memory provides density upgrades from 64-Mbit through 512- Mbit. This family of devices provides ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 1: Flash Die Virtual Chip Enable Truth Table for 512 Mbit QUAD+ Package Die Selected Lower Param Die Upper Param Die Table 2: Flash Die Virtual Chip Enable Truth Table for 512 Mbit ...
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Package Information 3.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A Standoff ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Count N Lead Tip Angle ý Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package ...
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Table 4: 64-Mbit and 128-Mbit Easy BGA Package Dimensions (Sheet Product Information Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 5: 256-Mbit and 512-Mbit Easy BGA Package Dimensions Product Information Package Height (256-Mbit) Package Height (512-Mbit) Ball Height Package Body Thickness (256-Mbit) Package Body Thickness (512-Mbit) Ball (Lead) Width Package Body Width Package ...
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QUAD+ SCSP Packages Figure 4: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark Top View - Ball Down A ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 5: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball ...
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Figure 6: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package Height ...
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Numonyx™ StrataFlash Embedded Memory (P33) 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout Figure 7: 56-Lead TSOP Pinout (64/128/256/512-Mbit) 1 A16 A15 2 3 A14 4 A13 5 A12 6 A11 7 A10 A23 10 A22 ...
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Figure 8: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 DQ10 ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 9: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin A18 C A5 RFU D A3 A17 DQ8 H ...
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Table 6: TSOP and Easy BGA Signal Descriptions Symbol Type ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[MAX:1] Input A[24:1]; 512-Mbit: A[25:1]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 7: QUAD+ SCSP Signal Descriptions Symbol Type ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[MAX:0] Input A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in ...
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Dual Die SCSP Configurations Figure 10: 512-Mbit Easy BGA / TSOP Top or Bottom Parameter Block Diagram Easy BGA/TSOP 512-Mbit (2-Die) Top or Bottom Parameter Configuration CE# WP# OE# WE# CLK ADV# A[MAX:1] Figure 11: 512-Mbit QUAD+ SCSP Top ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 8: Discrete Top Parameter Memory Maps (all packages) Size Blk (KB 3FC000 - 3FFFFF 32 63 3F0000 - 3F3FFF 128 62 3E0000 - 3EFFFF 128 56 380000 - 38FFFF 128 55 ...
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Table 9: Discrete Bottom Parameter Memory Maps (all packages) Size Blk (KB) 128 10 070000 - 07FFFF 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF 32 0 000000 - 003FFF Size Blk (KB) 128 258 FF0000 - FFFFFF ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 10: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA, TSOP, and QUAD+ SCSP) (Sheet Die Stack Config 256-Mbit Bottom Parameter Die Note: Refer to the appropriate 256-Mbit Memory Map ...
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Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Table 11: Absolute Maximum Ratings Parameter Temperature under bias Storage temperature Voltage ...
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Numonyx™ StrataFlash Embedded Memory (P33) 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 13: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], LO WAIT Current 64-Mbit 128-Mbit I , ...
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Table 13: DC Current Characteristics (Sheet Sym Parameter I V Program Current PPW Erase Current PPE PP Notes: 1. All currents are RMS unless noted. Typical values at typical the ...
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Numonyx™ StrataFlash Embedded Memory (P33) 7.0 AC Characteristics 7.1 AC Test Conditions Figure 12: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to ...
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Capacitance Table 16: Capacitance Symbol Parameter Address, Data, CE#, WE#, OE#, C Input Capacitance IN C Output Capacitance OUT Notes: 1. Capacitance values are for a single die; for dual die, the capacitance values are doubled. 2. Sampled, not ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 17: AC Read Specifications - 130nm (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to ...
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Table 17: AC Read Specifications - 130nm (Sheet Num Symbol (5,6) Synchronous Specifications R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 15: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR 10=0, WAIT ...
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Figure 17: Asynchronous Page-Mode Read Timing R2 A[Max:2] [A] A[1:0] R101 R105 R105 ADV# R3 CE# [E] R4 OE# [G] R15 WAIT [T] R7 DATA [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR 10=0, WAIT asserted low). Figure ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 19: Continuous Burst Read, showing an Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] ...
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AC Write Specifications Table 19: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data setup ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 21: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 22: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] ...
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Figure 23: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [E} WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 24: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [ A] R105 ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 25: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per ...
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Table 20: Program and Erase Specifications Num Symbol Parameter W500 t 32-KByte Parameter ERS/PB Erase Time W501 t 128-KByte Main ERS/MB W600 t Program suspend SUSP/P Suspend W601 t Erase suspend SUSP/E Latency W602 t Erase to Suspend ERS/SUSP Notes: ...
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Numonyx™ StrataFlash Embedded Memory (P33) 8.0 Power and Reset Specifications 8.1 Power-Up and Power-Down Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise V and V should attain their minimum operating voltage before ...
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Figure 26: Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high 8.3 Power Supply Decoupling ...
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Numonyx™ StrataFlash Embedded Memory (P33) 9.0 Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates ...
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Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, I measured over any ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 23: Command Bus Cycles Mode Command Read Array Read Device Identifier Read CFI Query Read Status Register Clear Status Register Word Program (3) Program Buffered Program Buffered Enhanced Factory (4) Program (BEFP) Erase ...
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Command Definitions Table 24 shows valid device command codes and descriptions. Table 24: Command Codes and Definitions (Sheet Mode Code Device Mode 0xFF Read Array Read Status 0x70 Register Read Device ID 0x90 or Configuration Read ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 24: Command Codes and Definitions (Sheet Mode Code Device Mode 0x60 Lock Block Setup 0x01 Lock Block Block Locking/ Unlocking 0xD0 Unlock Block 0x2F Lock-Down Block Program Protection Protection 0xC0 ...
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Device Operations This section provides an overview of device operations. The system Central Processing Unit provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip WSM manages all block-erase and ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 25: Status Register Description (Sheet Status Register (SR) 2 Program Suspend Status (PSS) 1 Block-Locked Status (BLS) 0 BEFP Write Status (BWS) Note: Always clear the Status Register prior to ...
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Table 26: Read Configuration Register Description (Sheet Wait Polarity (WP) 10 Data Hold (DH Wait Delay (WD) Burst Sequence (BS) 7 Clock Edge (CE) 6 5:4 Reserved (R) Burst Wrap (BW) 3 2:0 Burst Length ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 27: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ ...
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Figure 28: Example Latency Count Setting Using Code 3 CLK CE# ADV# A[MAX:0] D[15:0] 11.1.0.4 WAIT Polarity The WAIT Polarity bit (WP), RCR 10 determines the asserted level (V When WP is set, WAIT is asserted high (default). When WP ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 28: WAIT Functionality Table (Sheet Condition All Asynchronous Reads All Writes Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts. 2. When OE during writes, ...
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Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. lengths, as well as the effect of the Burst Wrap (BW) setting. Table 29: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word ...
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Numonyx™ StrataFlash Embedded Memory (P33) 11.1.0.11 Burst Length The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous ...
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To perform an asynchronous page-mode read, an address is driven onto the address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 30: Device Identifier Information (Sheet Item 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. BBA = Block Base Address. Table 31: ...
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Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device. This is followed by a second write to the device with the address and data to be programmed. The device outputs Status ...
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Numonyx™ StrataFlash Embedded Memory (P33) available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see On the next ...
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With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post-program verification and its associated overhead. 11.3.3.1 BEFP Requirements and Considerations BEFP requirements: • Case ...
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Numonyx™ StrataFlash Embedded Memory (P33) stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less ...
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During a program suspend, deasserting CE# places the device in standby, reducing active current. V unchanged while in program suspend. If RST# is asserted, the device is reset. 11.3.5 Program Resume The Resume command instructs the device to continue programming, ...
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Numonyx™ StrataFlash Embedded Memory (P33) During a block erase, the WSM executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits ...
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Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 11.4.6 Block Locking Individual instant block locking is used to protect user ...
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Numonyx™ StrataFlash Embedded Memory (P33) 11.4.6.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 11.2.3, “Read Device Identifier” on page addressed block’s lock status; DQ0 is the addressed block’s ...
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Selectable One-Time Programmable Blocks Blocks from the main array may be optionally configured as OTP. Ask your local Numonyx representative for details about any of the following selectable OTP implementations. 11.4.7.1 Permanent Block Locking 512 KB ...
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Numonyx™ StrataFlash Embedded Memory (P33) The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as ...
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Next, perform a read operation using the address offset corresponding to the register to be read. address offsets of the Protection Registers and Lock Registers. PR data is read 16 bits at a time. 11.4.8.2 Programming the Protection ...
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Numonyx™ StrataFlash Embedded Memory (P33) 12.0 Flowcharts Figure 33: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[7] = Suspend? 1 Full Status Check (if desired) Program Complete Read ...
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Figure 34: Program Suspend/Resume Flowchart Start Read Status Write 70h Program Suspend Write B0h Any Address Read Status Register 0 SR SR.2 = Completed 1 Read Array Write FFh Read Array Data Done No Reading Yes Program ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 35: Buffer Program Flowchart Start Device Use Single Word Supports Buffer No Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read ...
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Figure 36: BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Start V applied PP Block Unlocked W rite 80h @ st 1 Word Address W rite D0h @ st 1 Word Address BEFP Setup delay Read Status Reg. ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 37: Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register Suspend 0 SR[7] = Erase 1 Full Erase Status Check (if desired) Block ...
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Figure 38: Erase Suspend/Resume Flowchart Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register SR SR Read Read or Program Program ? Read Array No Data Done? Yes Erase ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 39: Block Lock Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change ? Yes ...
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Figure 40: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status ...
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Numonyx™ StrataFlash Embedded Memory (P33) 13.0 Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read ...
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Table 34: Example of Query Structure Output of x16- Devices Word Addressing: Offset Hex Code A – 00010h 0051 00011h 0052 00012h 0059 P_ID 00013h LO P_ID 00014h HI P 00015h LO P 00016h HI 00017h A_ID LO ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 37: System Interface Information Offset Length 1Bh 1 V logic supply minimum program/erase voltage CC bits 0–3 BCD 100 mV bits 4–7 BCD volts 1Ch 1 V logic supply maximum program/erase voltage CC ...
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Device Geometry Definition Table 38: Device Geometry Definition Offset Length 1 27h 28h 2 2 2Ah 2Ch 1 4 2Dh 4 31h 35h 4 A ddress 27: 28: 29 2B: 2C: 2D: 2E: 2F: 30: 31: 32: ...
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Numonyx™ StrataFlash Embedded Memory (P33) 13.4 Numonyx-Specific Extended Query Table Table 39: Primary Vendor-Specific Extended Query (1) Length Offset P = 10Ah (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ...
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Table 40: Protection Register Information (1) Length Offset P = 10Ah (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h (P+13)h 10 (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h Table 41: Burst Read Information (1) Length Offset P = 10Ah ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 42: Partition and Erase Block Region Information (1) Offset P = 10Ah Bottom Top Number of device hardware-partition regions within the device single hardware partition device (no fields follow). ...
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Table 44: Partition Region 1 Information (Sheet (1) Offset P = 10Ah Bottom Top (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0– y identical-size erase blks in ...
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Numonyx™ StrataFlash Embedded Memory (P33) Table 45: Partition and Erase Block Region Information Address 64-Mbit –B 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --03 137: --00 138: ...
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Table 46: CFI Link Information (1) Length Offset P = 10Ah CFI Link Field bit definitions (P+48)h 4 (P+49)h Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table (P+4A)h Bits 10–27 = nth 32Mbit segment of referenced ...
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Numonyx™ StrataFlash Embedded Memory (P33) 14.0 Write State Machine Figure 41 through based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read ...
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Figure 42: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend in ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 43: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) OTP Ready Setup Ready Lock/CR Setup (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend ...
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Figure 44: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) Setup Busy Word Program in Erase Suspend Suspend Setup BP Load 1 BP Confirm if Data load into Program Buffer is BP ...
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Numonyx™ StrataFlash Embedded Memory (P33) Figure 45: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Current chip state Setup (3,4) (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, ...
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Figure 46: Write State Machine—Next State Table (Sheet Output Next State Table OTP Setup Current chip state (C0H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word ...
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Numonyx™ StrataFlash Embedded Memory (P33) 7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the ...
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Appendix A Additional Information Order/Document Document/Tool Number 317460 Numonyx™ StrataFlash Numonyx™ StrataFlash 314750 (P33) Conversion Guide Application Note 867 300783 Using Numonyx™ 308551 Numonyx™ StrataFlash Migration Guide for Numonyx™ StrataFlash 306667 Memory (P30/P33) Application Note 812 290737 Numonyx™ StrataFlash 252802 ...
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... PC = 64- Ball Easy BGA , lead- free Product Line Designator Intel® Flash Memory Device Density 640 = 64- Mbit 128 = 128- Mbit 256 = 256- Mbit Table 47: Valid Combinations for Discrete Products - 130nm 64-Mbit RC28F640P33T85 RC28F640P33B85 PC28F640P33T85 PC28F640P33B85 TE28F640P33T85 TE28F640P33B85 JS28F640P33T85 JS28F640P33B85 November 2007 ...
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Appendix C Ordering Information for SCSP Products Figure 48: Decoder for SCSP Devices Package Designator ® Intel SCSP, leaded ® Intel SCSP, lead- free RC = 64- Ball Easy BGA , leaded PC ...