SII1160CTU Silicon image, SII1160CTU Datasheet
SII1160CTU
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SII1160CTU Summary of contents
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Technology SiI 1160 PanelLink Transmitter Data Sheet Document # SiI-DS-0126-B ® ...
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... Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. ...
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SiI 1160 PanelLink Transmitter Data Sheet General Description........................................................................................................................................ 1 Features ...................................................................................................................................................... 1 Functional Description .................................................................................................................................... 3 Electrical Specifications .................................................................................................................................. 4 Absolute Maximum Conditions ................................................................................................................... 4 Normal Operating Conditions ..................................................................................................................... 4 Digital I/O Specifications ............................................................................................................................. 4 DC Specifications........................................................................................................................................ 5 AC Specifications ...
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Table 1. General I C Register Bits................................................................................................................ 13 2 Table 2. Dual Zone PLL I C Control Register Bits ........................................................................................ 14 Table 3. One Pixel/Clock Input/Output TFT Mode........................................................................................ 15 Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 16 Table ...
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SiI 1160 PanelLink Transmitter Data Sheet General Description The SiI 1160 transmitter uses PanelLink Digital technology to support displays up to UXGA resolution. It supports up to true-color panels (24 bits per pixel, 16.7M colors pixels-per-clock ...
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its ...
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SiI 1160 PanelLink Transmitter Data Sheet Functional Description The SiI 1160 DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 48 bits for data input to allow for panel support up to UXGA. Figure 3 ...
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Electrical Specifications Absolute Maximum Conditions Symbol 1 V Supply Voltage 3. Input Voltage Input Voltage O T Junction Temperature (with power applied Storage Temperature STG Note 1. Permanent device damage may occur if ...
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SiI 1160 PanelLink Transmitter Data Sheet DC Specifications Under normal operating conditions, with R specified. Symbol Parameter V Differential Voltage OD Single ended peak to peak amplitude V Differential High-level Output DOH 1 Voltage I Differential Output Short DOS 1 ...
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Input Timing Diagrams 80% VCC IDCK D[23:0], DE, HSYNC,VSYNC DE VSYNC, HSYNC, CTL[3:1] Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE 80% VCC DE SiI-DS-0126-B T CIP T CIH 80% VCC 20% VCC Figure 4. Clock Cycle High/Low ...
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SiI 1160 PanelLink Transmitter Data Sheet VCC max VCC min VCC ISEL/RST Figure 8. Reset Timing at Power-Up or Prior to First I T RESET 7 T RESET 2 C Access SiI-DS-0126-B ...
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Pin Descriptions Input Pins Pin Name Pin # Type DIE23- See In SiI 1160 DIE0 Pin Diagram DIO23- See In DIO0 SiI 1160 Pin Diagram IDCK HSYNC 76 In VSYNC 77 In Control and Configuration ...
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SiI 1160 PanelLink Transmitter Data Sheet Power Management Pins Pin Name Pin # Type Differential Signal Data Pins Pin Name Pin # Type TX0+ 40 Analog TX0- 39 Analog TX1+ 43 Analog TX1- 42 Analog TX2+ 46 ...
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Reserved Pins It is preferable to tie indicated pins HIGH through a 2-5KΩ resistor; direct connection to VCC is not recommended. Pin Name Pin # Type RSVD 22 In RSVD 28 In RSVD 29 In RSVD 38 -- Power and ...
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SiI 1160 PanelLink Transmitter Data Sheet Feature Information Interface 2 The SiI 1160 Tx provides slave interface for more precise control of the chip features. Use of this interface is optional and is selected ...
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I C Register Mapping Addr. Bit 7 Bit 6 Bit 5 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 RSVD 0x8 write to 00 0x9 0xA 0xB- 0xD RSVD EZONE 0xE write to 00 0xF Notes: 1. Hexadecimal values ...
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SiI 1160 PanelLink Transmitter Data Sheet Register Name Access RO Vendor ID Low byte (0x01) VND_IDL RO Vendor ID High byte (0x00) VND_IDH RO Device ID Low byte (0x06) DEV_IDL RO Device ID High byte (0x00) DEV_IDH RO Device Revision ...
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Automatic Zone Control For applications that are not able to program the I circuit. This circuit determines whether the input pixel clock is operating in the low frequency range or the high frequency range, and sets the PLL zone selection ...
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SiI 1160 PanelLink Transmitter Data Sheet TFT Panel Data Mapping The following TFT data mapping tables are strictly listed for single link TFT applications only. For DSTN mapping please refer to Application Note SiI-AN-0007-A. SiI 1151 and SiI 1161 have ...
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Table 4. Two Pixels/Clock Input/Output TFT Mode TFT VGA Output 24-bpp 18-bpp ...
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SiI 1160 PanelLink Transmitter Data Sheet Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode TFT VGA Output 24-bpp ...
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Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode TFT VGA Output 18-bpp Shift CLK VSYNC HSYNC DE ...
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SiI 1160 PanelLink Transmitter Data Sheet Table 7. Two Pixels/Clock Input with One Pixel/Clock Output TFT Mode TFT VGA Output 24-bpp 18-bpp ...
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Design Recommendations Differences Between SiI 160 and SiI 1160 The SiI 1160 pin-compatible upgrade to the SiI 160 Tx. It provides improved cable length support without any changes to the pinout. Interrupt capability is also a new ...
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SiI 1160 PanelLink Transmitter Data Sheet Spread Spectrum Support TMDS architecture is inherently jitter-tolerant. Spread spectrum clocking can be applied to the clock and parallel data inputs of the SiI 1160 to allow for reduced EMI. The spread will be ...
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Reset Circuit for I C Application 2 If the design uses the I C interface to control the transmitter features, it must also provide a means of toggling the ISEL/RST pin to achieve the correct T easiest way to ...
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SiI 1160 PanelLink Transmitter Data Sheet Decoupling Capacitors Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown schematically in Figure 15. Place these components as close as possible to the PanelLink device ...
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... Source termination suppresses signal reflection to prevent non-DVI compliant receivers from erroneously sampling the TMDS signals at high frequencies (beyond 135MHz). The impact on DVI compliant receivers is minimal. Therefore Silicon Image recommends source termination for most applications. Note that the capacitor is required to meet DVI idle mode DC offset requirements and must not be omitted. Note also that the signal suppression requires the R Power consumption will be slightly higher when using source termination ...
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SiI 1160 PanelLink Transmitter Data Sheet Figure 18. Source Termination Layout Illustration The layout in Figure 18 has been developed to minimize trace stubs on the differential TMDS lines, while providing pads for the source termination components (left-hand magnified view). ...
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TX Figure 19. Example of Incorrect Differential Signal Routing TX Figure 20. Example of Correct Differential Signal Routing Figure 21. Differential Trace Routing to DVI Connector (Top Side View) SiI-DS-0126 SiI 1160 PanelLink ...
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SiI 1160 PanelLink Transmitter Data Sheet In addition to following the trace routing recommendations, length differences between intra-pair traces listed in column 2 of Table 11 and inter-pair traces listed in column 3 of Table 11, should be controlled to ...
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... Lot # YYWW Date Code TTTTTTm Trace Code c e Figure 22. 100-pin TQFP Package Dimensions (JEDEC code MS-026-AED) Ordering Information Standard Part Number: SiI1160CTU (‘U’ indicates Universal package usable in both standard and lead-free environments) SiI-DS-0126 SiI 1160 PanelLink Transmitter ...
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... SiI 1160 PanelLink Transmitter Data Sheet © 2005 Silicon Image. Inc. SiI-DS-0126-B Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA Tel: (408) 616-4000 Fax: (408) 830-9530 E-mail: salessupport@siimage.com Web: www.siliconimage.com 29 SiI-DS-0126-B ...