QL3025-1PF144C QULOG, QL3025-1PF144C Datasheet
QL3025-1PF144C
Related parts for QL3025-1PF144C
QL3025-1PF144C Summary of contents
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... QL3025 pASIC 3 FPGA Data Sheet • • • • • • 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density 25,000 Usable PLD Gates with 204 I/Os • 300 MHz 16-bit Counters, • ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E Architecture Overview The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic patented ViaLink density, low cost, and extreme ease-of-use. The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is ...
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... Hold Time 0.0 Clock to Q Delay 0.7 Clock High Time 1.2 Clock Low Time 1.2 Set Delay 1.0 Reset Delay 0.8 Set Width 1.9 Reset Width 1.8 Table 7 . Table 2: Input-Only/Clock Cells Parameter Propagation Delays (ns) Fanout 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Table 7 . QL3025 pASIC 3 FPGA Data Sheet Rev E by the numbers provided Table 1.7 1.9 2.2 3.2 1.7 1.7 1.7 1.7 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1 ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E Symbol t Array Clock Delay ACK t Global Clock Pin Delay GCKP t Global Clock Buffer Delay GCKB a. The array distributed networks consist of 40 half columns and the global distributed networks con- sist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay ...
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... The following loads presented in © 2002 QuickLogic Corporation Table 5: Output-Only I/O Cells Propagation Delays (ns) Output Load Parameter 30 50 2.1 2.5 2.2 2.6 1.2 1.7 1.6 2.0 a 2.0 1.2 Figure 2 are used for t t PHZ 5 pF Figure 2: Loads used for t QL3025 pASIC 3 FPGA Data Sheet Rev E Capacitance (pF) 75 100 150 3.1 3.6 4.7 3.2 3.7 4.8 2.2 2.8 3.9 2.6 3.1 4 ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E DC Characteristics The DC specifications are provided in Parameter V Voltage CC V Voltage CCIO Input Voltage Latch-up Immunity Symbol V Supply Voltage CC V I/O Input Tolerance Voltage CCIO TA Ambient Temperature TC Case Temperature K Delay Factor • • • www.quicklogic.com 6 • • ...
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... V or GND I CCIO GND GND I IO CCIO CCIO for -0 commercial grade and all CC Contact Information ). QL3025 pASIC 3 FPGA Data Sheet Rev E Min Max Units 0 0 CCIO -0.5 0 2 0. -10 10 µA ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E Kv and Kt Graphs 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 • • • www.quicklogic.com 8 • • • Voltage Factor vs. Supply Voltage 3 3.1 3.2 3.3 Supply Voltage (V) Figure 3: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1 ...
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... Time Figure 5: Power-up Requirements when ramping the device. CC earlier than 400 µs can cause the device to behave improperly. and Figure 6: Internal Diode Between V QL3025 pASIC 3 FPGA Data Sheet Rev E ≤ 500 mV. Deviation from CCIO CC MAX . Ramping shown in ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E JTAG TCK TMS TRSTB RDI Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149 ...
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... TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. © 2002 QuickLogic Corporation QL3025 pASIC 3 FPGA Data Sheet Rev E The Extest instruction performs a PCB interconnect test. This test This instruction allows a device to remain in its The Bypass instruction allows data to skip a device's boundary • ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E Pin Descriptions Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I CCIO GND Ordering Information QuickLogic device pASIC 3 device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow * Contact QuickLogic regarding availability. (See • ...
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... Pin 1 Pin 37 208 PQFP Pinout Diagram Pin 1 Pin 53 © 2002 QuickLogic Corporation QL3025 pASIC 3 FPGA Data Sheet Rev E pASIC 3 QL3025-1PF144C Figure 8: Top View of 144 Pin TQFP pASIC 3 QL3025-1PQ208C Figure 9: Top View of 208 Pin PQFP Pin 109 Pin 73 Pin 157 Pin 105 www.quicklogic.com • ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E 144 TQFP & 208 PQFP Pinout Table 208 144 208 Function PQFP TQFP PQFP GND ...
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... PBGA Pinout Diagram © 2002 QuickLogic Corporation pASIC 3 QL3025-1PB256C BOTTOM View Figure 10: 256-Pin PBGA Pinout Diagram QL3025 pASIC 3 FPGA Data Sheet Rev E PIN A1 CORNER www.quicklogic.com • • • 15 • • • ...
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... QL3025 pASIC 3 FPGA Data Sheet Rev E 256 PBGA Pinout Table 256 Function PBGA A1 VSS A2 I/O A3 I/O A4 I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 TCK A20 I/O B1 TDO B2 I/O B3 I/O B4 I/O B5 I/O B6 I/O B7 I/O B8 I/O B9 I/O B10 I/O B11 I/O B12 I/O B13 I/O B14 I/O B15 ...
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... Table 12: Revision History Date Comments not avail. First release. not avail. not avail May 2001 Update of AC/DC Specs and reformat Added Kfactor, Power-up, JTAG and mechanical June 2002 drawing information. Reformatted. QL3025 pASIC 3 FPGA Data Sheet Rev E www.quicklogic.com • • • 17 • • • ...