GL811usB GENES, GL811usB Datasheet
GL811usB
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GL811usB Summary of contents
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... GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller Specification 1.3 May 10, 2002 Genesys Logic, Inc. 10F, No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan Tel: 886-2-2664-6655 Fax: 886-2-2664-5757 http://www.genesyslogic.com Genesys Logic, Inc. ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 1. General Description ......................................................................................... 2 2. Features ............................................................................................................ 3 3. Function Block ................................................................................................. 4 3.1 Block Diagram .............................................................................................. 4 3.2 Functional Overview ..................................................................................... 5 4. Pinning Information ......................................................................................... 7 4.1 Pin Assignment............................................................................................. 7 4.2 Pin Description ............................................................................................. 8 5. Functional Description .................................................................................. 10 5.1 ATA/ ATAPI ................................................................................................. 10 5.2 USB 2.0 ...................................................................................................... 10 6. Electrical Characteristics .............................................................................. 11 6.1 Absolute Maximum Ratings ........................................................................ 11 6.2 Temperature Conditions ............................................................................. 11 6.3 DC Characteristics...................................................................................... 11 6 ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 1. General Description The GL811USB is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver one-chip solution which complies with Universal Serial Bus specification rev. ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 2. Features Complies with Universal Serial Bus specification rev. 2.0. Complies with ATA/ATAPI-6 specification rev 1.0. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X. Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3) ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3. Function Block 3.1 Block Diagram DMACK_ CLK15 DIOR_ DIOW_ CS1_, CS0_ 8 DA2 DA1 DA0 8/16-Bit IODD15-0 IDE INTRQ 4 CBLID_ Engine DMARQ IORDY 12-96MHz X10 Clkgen 12MHz X40 ©2000-2002 Genesys Logic Inc.—All rights reserved. CPU ...
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... UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO. 3.2.6 CPU The CPU is the control center of GL811USB. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response proper data/status to USB host ...
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... FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to IDE engine. 3.2.9 Control Registers Control Register configures GL811USB to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host. ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 4. Pinning Information 4.1 Pin Assignment GPIO7 1 IODD[8] 2 IODD[9] 3 IODD[10] 4 IODD[11] 5 DVCC1 6 DGND1 7 IODD[12] 8 IODD[13] 9 IODD[14] 10 IODD[15] 11 CBLID_ 12 ©2000-2002 Genesys Logic Inc.—All rights reserved. GL811USB 48 LQFP DIOW_ 36 DIOR_ 35 IORDY 34 DMACK_ 33 INTRQ 32 DA1 31 DA0 30 CS0_ 29 TEST ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 4.2 Pin Description Pin # Name 1 GPIO7 2~5 IODD [8:11] 6 DVCC1 7 DGND1 8~11 IODD [12:15] 12 CBLID_ 13 CS1_ 14 DA2 15 RESET# 16 RPU 17 AVCC0 18 DPF 19 DPH 20 DMF 21 DMH 22 AGND0 23 RREF 24 AVCC1 AGND1 28 TEST 29 CS0_ 30 DA0 31 DA1 32 INTRQ 33 DMACK_ 34 IORDY 35 DIOR_ 36 DIOW_ ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller Pin # Name 38~41 IODD[0:3] 42 DGND2 43 DVCC2 44~47 IODD[4:7] 48 GPIO1 (*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of I/O 8 type is 8 mA, and for I/O pad mA. (**) When operating in default mode: GPIO7 is the ATA/ ATAPI reset input, (***) When Reset pin is pulled low, the IDE bus will be in tri-state ...
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... The GL811USB complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information. 5.2 USB 2.0 The GL811USB complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI) specification rev. 1.01. Please refer to the specifications for more information. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol V DC supply voltage input voltage input voltage range for I/O I input voltage for USB D+/D- pins AI/O V Static discharge voltage ESD T Ambient Temperature A 6.2 Temperature Conditions Item Storage Temperature Operating Temperature 6 ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller Parameter Hysteresis voltage Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister Pad internal pull up resister Supply current 6.3.2 I/O 16 Type digital pins (For pad type I Parameter Current sink @ ...
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... D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading 6.4 AC Characteristics- ATA/ ATAPI The GL811USB complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. PIO (Programmed Input/ Output) data transfer: PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller - - - - - - - All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.1 Register transfers ADDR valid (Note1) DIOR_/DIOW_ WRITE IODD(7:0) (Note2) Read IODD(7:0) (Note2) IORDY (Note3.1) IORDY (Note3.2) IORDY (Note3.3) Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle extended is made by the host after t assertion of DIOR_ or DIOW_ ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before t released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before t asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2 Multiword DMA data transfer Multiword DMA timing parameters t Cycle time 0 t DIOR_/ DIOW_ asserted pulse width D t DIOR_ data access E t DIOR_ data hold F t DIOR_/ DIOW_ data setup G t DIOW_ data hold H t DMACK to DIOR_/ DIOW_ setup ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.1 Initiating a Multiword DMA data burst CS0_/ CS1_ (Note) DMARQ (Note) DMACK_ DIOR_/DIOW_ Read DD(15:0) Write DD(15:0) Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.2 Sustaining a Multiword DMA data burst CS0_/ CS1_ DMARQ DMACK_ DIOR_/DIOW_ Read DD(15:0) Write DD(15:0) ©2000-2002 Genesys Logic Inc.—All rights reserved Page 19 ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.3 Device terminating a Multiword DMA data burst CS0_/ CS1_ DMARQ (Note) DMACK_ DIOR_/DIOW_ Read DD(15:0) Write DD(15:0) Note: To terminate the data burst, the Device shall negate DMARQ within the t current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.4 Host terminating a Multiword DMA data burst CS0_/ CS1_ DMARQ (Note2) DMACK_ (Note1) DIOR_/DIOW_ Read DD(15:0) Write DD(15:0) Note terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3 Ultra DMA data transfer 6.4.3.1 Ultra DMA data burst timing requirements Mode 0 Mode 1 Name (in ns) (in ns) min max min t 240 160 2CYCTYP t 112 73 CYC t 230 154 2CYC DVS DVH ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.2 Initiating an Ultra DMA data-in burst DMARQ (device) DMACK_ (host) STOP (host) HDMARDY_ (host) DSTROBE (device) IODD (15:0) DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.3 Sustained Ultra DMA data-in burst DSTROBE at device t DVH IODD(15:0) at device DSTROBE at host t IODD(15: host Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.4 Host pausing an Ultra DMA data-in burst DMARQ (device) DMACK_ (host) STOP (host) HDMARDY_ (host) DSTROBE (device) IODD(15:0) (device) Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY_ is negated. ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.5 Device terminating an Ultra DMA data-in burst DMARQ (device) DMACK_ (host) STOP (host) HDMARDY_ (host) t DSTROBE SS (device) IODD(15:0) DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.6 Host terminating an Ultra DMA data-in burst DMARQ (device) DMACK_ (host) t STOP RP (host) HDMARDY_ (host) t RFS DSTROBE (device) IODD(15:0) DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.7 Initiating an Ultra DMA data-out burst DMARQ (device) DMACK_ (host) STOP (host) DDMARDY_ (device) HSTROBE (host) IODD (15:0) (host) t DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.8 Sustained Ultra DMA data-out burst HSTROBE at host t DVH IODD(15:0) at host HSTROBE at device t IODD(15: device Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.9 Device pausing an Ultra DMA data-out burst DMARQ (device) DMACK_ (host) STOP (host) DDMARDY_ (device) HSTROBE (host) IODD(15:0) (host) Notes: 1.The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY_ is negated. ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.10 Host terminating an Ultra DMA data-out burst DMARQ (device) DMACK_ (host STOP (host) DDMARDY_ (device) HSTROBE (host) IODD(15:0) (host) DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.11 Device terminating an Ultra DMA data-out burst DMARQ (device) DMACK_ (host) STOP (host) DDMARDY_ (device) t RFS HSTROBE (host) IODD(15:0) (host) DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. © ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.5 AC Characteristics- USB 2.0 The GL811USB conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 33 ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 7. Package Dimension SYMBOL ©2000-2002 Genesys Logic Inc.—All rights reserved. MIN MAX 1.6 0.05 0.15 1.35 1.45 0.09 0.16 9.00BSC 7.00BSC 9.00BSC 7.00BSC 0.5BSC 0.17 0.27 0.45 0.75 1 REF Page 34 ...
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... GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 8. Revision History Version 1.0 First draft 1.1 Correct the pin assignment GPIO1/ CPIO7 for 48-pin package Electrical Characteristics data supplement, and eliminate the 1.2 100-pin LQFP package. 1.3 AC Characteristics (ATA/ ATAPI) data supplement in Chapter 6. 2002/05/10 ©2000-2002 Genesys Logic Inc.—All rights reserved. ...