LXT305APE Level-One-Communications, LXT305APE Datasheet
LXT305APE
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LXT305APE Summary of contents
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Data received for transmission onto the line is clocked seri- ally into the device at TPOS and TNEG. Input synchroni- zation is supplied by the transmit clock (TCLK). The transmitted pulse shape is determined by Equalizer Control signals EC1 ...
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To allow a host microprocessor to access and control the LXT305A through the serial interface, MODE is set High. The serial interface (SDI/SDO) uses a 16-bit word consist- ing of an 8-bit Command/Address byte and an 8-bit ...
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The LXT305A serial port is addressed by setting bit A4 in the Address/Command byte, corresponding to address 16. The LXT305A contains only a single output data register so no complex chip addressing scheme is required. The register is accessed by ...
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