GLT5160L16-7TC G-Link Technology Corporation, GLT5160L16-7TC Datasheet
GLT5160L16-7TC
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GLT5160L16-7TC Summary of contents
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... ESCRIPTION The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchro- nous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The GLT5160L16 achieves u Column access - random u Auto precharge / All bank precharge controlled by A[10] u Auto refresh and Self refresh ...
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G -LINK UNCTIONAL LOCK IAGRAM A[10:0] Address Buffer BA CLK Clock Buffer CKE CS RAS CAS Control Signal Buffer WE DQML DQMU Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM Signal Description Signal Type CLK ...
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... F D UNCTIONAL ESCRIPTION The GLT5160L16 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of RAS, CAS and WE at CLK rising edge. In addition to 3 signals, CS, CKE and A[10] are used as chip select, refresh option, and precharge option, respectively ...
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G -LINK [1] [2] Function Truth Table Current State CS RAS CAS IDLE ROW ACTIVE ...
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G -LINK [1] [2] Function Truth Table (Continued) Current State CS RAS CAS READ with AUTO H X PRECHARGE WRITE with AUTO H X ...
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G -LINK [1] [2] Function Truth Table (Continued) Current State CS RAS CAS REFRESHING MODE REGISTER H X SETTING ...
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G -LINK [1] Function Truth Table for CKE CKE n- Current State 1 CKE n [2] SELF-REFRESH POWER DOWN [3] ...
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G -LINK Power On Sequence Before starting normal operation, the following power on sequence is necessary to prevent damage or malfunction. 1. Apply power and start clock. Attempt to maintain CKE high, DQMU / DQML high and NOP condition at ...
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G -LINK Mode Register Burst Length, Burst Type and CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in ...
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G -LINK O D PERATIONAL ESCRIPTION Bank Activate The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address (BA). A row is indicated by the row address A[10:0] The minimum activation interval ...
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G -LINK Read After t from the bank activation, a READ command can be RCD issued. 1st output data is available after the CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The ...
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G -LINK Write After t from the bank activation, a WRITE command can be RCD issued. 1st input data is set at the same cycle as the WRITE. Follow- ing (BL-1) data are written into the RAM, when the Burst ...
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... G -LINK Burst Interruption [Read Interrupted by Read] The burst read operation can be interrupted by a new read of the same or the other bank. GLT5160L16 allows random column access. READ to READ interval is 1 CLK minimum. CLK Command REA REA A[9: A[10 Figure 9. READ Interrupted by READ (BL=4, CL=3) ...
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G -LINK [Read Interrupted by Precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command disables the data output, depending on the CAS Latency. The figure ...
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G -LINK [Read Interrupted by Burst Terminate] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TBST interval is minimum 1 CLK. The figure below shows examples, when the data-out ...
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G -LINK [Write Interrupted by Write] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. CLK Command WRIT WRIT A[9:0] ...
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G -LINK [Write Interrupted by Precharge] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recov- ery time ( required between the last input data and the ...
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G -LINK Auto Refresh Single cycle of auto-refresh is initiated with a REFA (CS = RAS = CAS = CKE = H) command. The refresh address is gener- ated internally. 4096 REFA cycles within 64 ms refresh ...
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G -LINK CLK Suspend CKE controls the internal CLK at the following cycle. Figure 19 and Figure 20 show how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power ext. CLK ...
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G -LINK DQMU / DQML Control DQMU / DQML is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMU / DQML masks upper / lower input data word by ...
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G -LINK E S LECTRICAL PECIFICATIONS [1] Absolute Maximum Ratings Symbol Parameter V Supply Voltage DD V Supply Voltage for Output DDQ V Input Voltage I V Output Voltage O I Output Current O P Power Dissipation D T Operating ...
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G -LINK Average Supply Current from +70° 3.3 ±0 DDQ Symbol Parameter I Operating Current, Single Bank CC1S I Operating Current, Dual Bank CC1D I Standby ...
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... Output Hold Time from CLK OH t Delay Time, Output Low Impedance from OLZ CLK t Delay Time, Output High Imped- OHZ ance from CLK REF V + OUT ( For GLT5160L16-6/7, the Output Load 3.3 ±0 DDQ -6 -7 Min Max Min Max CL=2 - CL=3 5.5 2.5 2 CL=2 - CL=3 5.5 ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9:0] Xa A[10 ACT Figure 23. WRITE Cycle (single bank) BL=4 24 G-LINK Technology SEPT. 2004 (Rev. 2.7) t RDL t RAS t RC HIG ...
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G -LINK CLK t RCD CS t RRD RAS CAS WE CKE DQMU, A[9: A[10 Da0 ACT WRIT Figure 24. WRITE Cycle (Dual Bank) BL=4 t RDL t RCD t RAS t RAS ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9:0] Xa A[10 ACT Figure 25. READ Cycle (Single Bank) BL=4, CL=3 26 G-LINK Technology SEPT. 2004 (Rev. 2.7) t RAS Qa0 ...
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G -LINK t RCD CLK t RRD CS RAS CAS WE CKE DQMU, A[9: A[10 ACT READ Figure 26. READ Cycle (Dual Bank) BL=4, CL=3 t RCD t RAS t RAS ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9:0] Xa A[10 ACT Figure 27. WRITE to READ (Single Bank) BL=4, CL=3 28 G-LINK Technology SEPT. 2004 (Rev. 2.7) t RAS Ya Yb Da0 Da1 ...
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G -LINK t RCD CLK t RRD CS RAS CAS WE CKE DQMU, A[9: A[10 Da0 ACT WRITE Figure 28. WRITE to READ (Dual Bank) BL=4, CL=3 t RCD t RAS t RAS t WR ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQML DQMU A[9:0] Xa A[10 DQ[7:0] DQ[15:8] ACT Figure 29. DQM Byte Control for WRITE to READ (Single Bank) BL=4, CL=3 30 G-LINK Technology SEPT. 2004 (Rev. 2.7) ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9: A[10 PRE READ Figure 30. READ to WRITE (Single Bank) BL=4, CL=3 t RAS for output disable Yb Qa0 Qa1 Db0 Db1 Db2 ...
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G -LINK t RCD CLK t RRD CS RAS CAS WE CKE DQMU, A[9:0] Xa A[10 ACT Figure 31. READ to WRITE (Dual Bank) BL=4, CL=3 32 G-LINK Technology SEPT. 2004 (Rev. 2.7) t RCD t RAS ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9: A[10 Da0 ACT WRITE Figure 32. Write with Auto-Precharge BL RDL t RC Da1 Da2 Da3 Internal Precharge starts this ...
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G -LINK CLK t RCD CS RAS CAS WE CKE DQMU, A[9:0] Xa A[10 ACT Figure 33. Read with Auto-Precharge BL=4, CL=3 34 G-LINK Technology SEPT. 2004 (Rev. 2. Qa0 Qa1 Qa2 READ Internal ...
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G -LINK CLK RAS CAS WE CKE DQMU, A[9:0] A[10 any bank is active, it PRE must be precharged REF High Figure 34. Auto-Refresh REF G-LINK Technology 35 SEPT. 2004 ...
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G -LINK CLK RAS CAS WE CKE DQMU, A[9:0] A[10 any bank is active, it must be precharged PRE 36 G-LINK Technology SEPT. 2004 (Rev. 2.7) REF S Figure 35. Self-Refresh Entry ...
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G -LINK CLK CS RAS CAS WE CKE t SRX DQMU, A[9:0] A[10 NOP or desel Internal CLK Re-start Figure 36. Self-Refresh Exit Xa Xa ACT G-LINK Technology 37 SEPT. 2004 (Rev.2.7) ...
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G -LINK CLK RAS CAS WE CKE DQMU, A[9:0] A[10 any bank is PRE active, it must be precharged Figure 37. Mode Register Set BL=4, CL=3 38 G-LINK Technology SEPT. 2004 (Rev. 2.7) t ...
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G -LINK P I ACKAGING NFORMATION Figure 38. 50-Pin 400 mil TSOP II Pin Assignment DQ0 2 49 DQ15 ...
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G -LINK P I ACKAGING NFORMATION G-LINK Technology SEPT. 2004 (Rev. 2. CLK CS DQ8 CKE DQ9 DQ10 A5 A6 ...
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G -LINK unit : mm G-LINK Technology 41 SEPT. 2004 (Rev.2.7) ...
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G -LINK A B 0.10(4X) 42 G-LINK Technology SEPT. 2004 (Rev. 2.7) Ø0.08 M Ø0. 0.65 3.90 6.40 ± 0.10 0.45 REF C 0.10 SEATING PLANE C 60-Ball VFBGA ( BOTTOM VIEW ) ...
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G -LINK 0.10(4x) C 0.10 C 48-Ball VFBGA ( BOTTOM VIEW ) Ø0. CORNER Ø0. Ø ...
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... G -LINK O I RDERING NFO GLT5160L16 Part Number Mode GLT5160L16-10TC Synchronous GLT5160L16-8TC Synchronous GLT5160L16-7TC Synchronous GLT5160L16-6TC Synchronous GLT5160L16-10FJ Synchronous GLT5160L16-8FJ Synchronous GLT5160L16-7FJ Synchronous GLT5160L16-6FJ Synchronous GLT5160L16-10FI Synchronous GLT5160L16-8FI Synchronous GLT5160L16-7FI Synchronous GLT5160L16-6FI Synchronous GLT5160L16I-10TC Synchronous GLT5160L16I-8TC Synchronous GLT5160L16I-7TC Synchronous GLT5160L16I-6TC Synchronous GLT5160L16I-10FJ ...
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G -LINK O I RDERING NFO Parts Numbers (Top Mark) Definition : GLT 5 160 DRAM -SRAM 5 : Synchronous DRAM 064 : 8K /Pseudo DRAM 256 : 256K 6 : Standard 512 : 512K SRAM ...
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... The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies. G-LINK www.glinktech.com G-LINK Technology Corporation, Taiwan 6F, No.24-2, Industry E.RD.IV, Science Based Industrial Park, Hsin Chu, Taiwan, R.O.C. ...