RTL8308B ETC-unknow, RTL8308B Datasheet
RTL8308B
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RTL8308B Summary of contents
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... Testing ........................................................ 21 6.23.1 External SRAM Test ........................... 21 6.23.2 Production Testing .............................. 21 6.23.3 Loopback............................................. 21 7. 24LC02 Serial EEPROM Format ................... 22 8. Electrical Characteristics................................. 23 8.1 Temperature Limit Ratings........................... 23 8.2 DC Characteristics........................................ 23 8.3 AC Characteristics........................................ 23 8.3.1 Reset and Clock Timing........................ 23 8.3.2 RMII Timing ......................................... 24 8.3.3 PHY Management Timing .................... 25 8.3.4 Serial EEPROM 24LC02 Timing ......... 26 9. Mechanical Information................................... 27 1 RTL8308B Rev. 2.0 ...
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... MDIO to external PHY Supports operation Provides an LED display to indicate network loop existence Reversible PHYAD order for diverse PHY usage 3.3V 24LC02 interface Optional EEPROM 24LC02 for Loop detect configuration 128-pin PQFP, 0.35 um, 3.3V CMOS technology 2 RTL8308B Half-duplex: back pressure Full-duplex: IEEE 802.3X Store-and-forward and Rev. 2.0 cut-through ...
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... Speed, duplex, link status and flow control can be acquired by periodically polling the status of the PHY devices via MDIO. The address look-up table consists entry hash table and a 128 entry CAM. The RTL8308B uses the address hashing algorithm or direct mapping method to search destination MAC addresses from and record source MAC addresses to the hash table ...
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... FIFOs Flow control 128-entry Address CAM 2002/01/23 8 Ports RMII 10/100 MAC FIFOs, QUEUE, Flow Control, RX/TX F.P.P. FIFO Address-Lookup Engine F.P.P FIFO 4 PHY EEPROM Management I/F I/F EDORAM Packet I/F Buffer Space DMA Engine Page Pointer Switching Space Logic 8K-entry Address Table Buffer Manager RTL8308B LED I/F Rev. 2.0 ...
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... GND 7 TXE[A] 8 TXD0[A] 9 TXD1[A] 10 CRSDV[A] 11 RXD0[A] 12 RXD1[A] 13 TXE[B] 14 TXD0[B] 15 TXD1[B] 16 VCC 17 VCC 18 CRSDV[B] 19 RXD0[B] 2002/01/23 RTL8308B 5 RTL8308B 83 GND 82 GND 81 RXD1[F] 80 RXD0[F] 79 CRSDV[F] 78 TXD1[F] 77 TXD0[F] 76 TXE[F] 75 GND 74 RXD1[E] 73 RXD0[E] 72 CRSDV[E] 71 GND 70 TXD1[E] 69 TXD0[E] 68 TXE[ VCC GND ...
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... IEEE 802.3 specifications. Loss of carrier will result in the deassertion of this pin, synchronous to the cycle of the reference clock, REFCLK. 11,12,19,20, Receive Data [1:0]: The RTL8308B captures the receive data 29,31,62,63, on the rising edge of REFCLK when CRSDV is asserted high. 73,74,80,81, When CRSDV is asserted high, RXD[1:0] will transition 90,91,97,98 synchronously to REFCLK ...
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... Reset: Active low to a known reset state. After power-on reset (low to high), the configuration modes from Mode Pins are determined. Then, the contents of the serial EEPROM is auto-loaded into and the RTL8308B, which begins to access the management data of PHY devices. 119 System clock input: The same 50 MHz clock as REFCLK is used ...
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... Loop Detected LED: Low active. This pin, asserted low indicates that a network loop is detected. 56 DRAM Test Output: For internal test use. Pin No 106 Test pin: For internal use. Must be tied to ground for normal operation. Pin No 6,21,22,23,30, 34,35,36,48, 49,64,71,75,82, 83,101,105,111, 115,116,126 16,17,25,39,40, 51,52,66,85,95, 103,109,113, 124,128 8 RTL8308B Description Description Description Rev. 2.0 ...
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... PHYs use the same reset signal source. The PHY reset must be completed before the RTL8308B. 6.2 Network Interface The RTL8308B has 8 10/100 Mbps Ethernet ports (port 0 to port 7) with Reduced MII (R-MII) interfaces. It has 1 MII port in addition to the 4 R-MII ports for 10/100Mbps Ethernet transceivers. Note that an MII interface operates at 25MHz in 100Mbps transmission and 2 ...
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... The RTL8308B provides a 10/100 Mbps low pin count RMII interface for use between PHY and RTL8308. The MAC of each port of RTL8308B is connected to the PHY through the standard RMII interface. The RMII is capable of supporting 10Mbps and 100Mbps data rates. A single clock reference, 50MHz, sourced from an external clock input is used for receiving and transmitting ...
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... MIB counter. The RTL8308B can handle frames up to 1536 bytes. All frames longer than 1536 byte will be discarded. If the port continues to receive data after the 1536th byte, the port’s data will be filtered. If the port is in half duplex mode, the port will no longer be able to transmit or receive data during the long packet reception ...
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... For a read operation, the RTL8308Bwill output a ‘10’ to indicate read operation after the start of frame indicator. The 5-bit ID address of the PHY device and the 5-bit register address is next. Then, the RTL8308Bwill stop driving the MDIO line, and wait for one bit time. During this time, the MDIO should high impedance state. ...
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... The source address retrieved from the received frame is automatically stored buffer. The RTL8308B will then check for error and security violation, and perform a SA search. If there is no error or security violation, the chip will store the source address in the address lookup table. If the SA has been previously stored in another port’ ...
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... CAM accordingly. Using this eliminates the hash collision problem. 6.8 Address Direct Mapping Mode In this mode, the RTL8308B uses the last 13 bits of the MAC address to index to the 8K-entry look-up table. 6.9 Frame Filtering The RTL8308B will make filtering and forwarding decisions for each packet received based on its packet routing table, VLAN Mapping, port state, and the system configuration ...
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... The page pointers are contained in Page Pointer Space. 6.13 Buffer Manager The Buffer Manager of the RTL8308B contains a Free Page Pointer FIFO pool to store and provide available free page pointers to all ports. After power up reset, the Buffer Manager will initiate the Descriptor Read command to get some available free page pointers from Page Pointer Space ...
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... Flood Control option (System Configuration register 00). If Flood Control is disabled, the packet will be forwarded to all ports (except the receiving port) within the same VLANs of the receiving port. If the FloodControl option is enabled, the RTL8308B will forward the packet only to the uplink port specified at the receiving port. ...
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... The RTL8308B can operate in cut-through or store-and-forward mode. When in cut through mode (by pulling the ENCUTHR pin high), if receiving packet length is greater than 512 bytes, the RTL8308B starts to forward it after 512 bytes are received. If less than 512 bytes, the RTL8308B operates as same as store-and-forward mode. ...
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... PC parallel port or 8051 controller) to program the 24LC02 contents 24LC02 is not used, byte 0 of the 24LC02 would be read as FF. When byte 0 is not FF, the RTL8308B will directly use the default value. The default values of byte 0 and byte 1 are 00. When the 24LC02 is not used, the RTL8308B will also use default SID, FCS of Pause-On and Pause-off ...
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... As long as the 24LC02 receives an acknowledgement, it will continue to increment the data word address and serially clock out sequential data words. *Start and Stop Definition SDA SCL START *Output Acknowledge SCL 1 DATA IN DATA OUT START 2002/01/23 STOP 8 9 ACKNOWLEDGE 19 RTL8308B Rev. 2.0 ...
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... Read DEVICE ADDRESS SDA DUMMY WRITE *Sequential Read DEVICE ADDRESS SDA 2002/01/23 WORD ADDRESS n DATA n DATA n+1 20 DEVICE ADDRESS DATA n DATA n+x RTL8308B Rev. 2.0 ...
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... Production Testing The RTL8308B supports a simple but effective testing function for final production test in the process of switch manufacturing. If board diagnostic function is enabled, the switch may act as a packet generator to be part of the production test fixture to test finished switch system on production line. In this mode, the switch generates 16 broadcast packets on each port, from port 0 to port 4/7 sequentially ...
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... When 0, address direct mapping algorithm used 24LC02 is used, the default values of byte 0 and byte 1 are 00, and the default SID is 0180c2000001. 2002/01/ AcceptErr Ethernet ID (Physical Address) PAR47~0 Pause ON CRC 31~0 Pause OFF CRC 31~0 Loop Detection CRC 31~0 22 RTL8308B PHYAD_RV Rev. 2.0 ...
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... I OUT= 0mA, Description t1 t2 Reset and Clock Timing 23 Maximum +125 70 Min. Typical 0.9 * Vcc 0.1 * Vcc 0.5 * Vcc Vcc+0.5 -0.5 0.3 * Vcc -1.0 -10 145 Min. Typical Max 1000 - - RTL8308B Units ˚C ˚C Max. Units Vcc 1.0 µA 10 µA 160 mA Units MHZ ns ns Rev. 2.0 ...
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... CSRDV,RXD to REFCLK rising setup time t7 CRSDV,RXD to REFCLK rising hold time REFCLK TXE TXD[1:0] REFCLK CRSDV RXD[1:0] 2002/01/23 Min. Typical - DATA RMII Transmit Timing DATA RMII Receive Timing 24 RTL8308B Max. Units - Rev. 2.0 ...
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... MDC to MDIO delay (Read Bits) t7 MDC/MDIO actives from RST# deasserted 2002/01/23 Min MDC t4 MDIO data MDIO Write Timing MDC MDIO MDIO Read Timing 25 Typical Max. SYSCK * - 32 SYSCK * - 16 SYSCK * - 94.377 - t5 t6 data RTL8308B Units Rev. 2.0 ...
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... SDA (input) RST# MDC MDIO 2002/01/23 Description VALID t8 t9 VALID t10 EEPROM Interface Timing t7 high high MDC/MDIO Reset Timing 26 Min. Typical - - VALID VALID RTL8308B Max. Units 66 kHZ - Rev. 2.0 ...
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... Controlling dimension: Millimeter 0.10 0.25 0.91 4. General appearance spec. should be based on final visual 2.60 2.85 3.10 inspection spec. 0.12 0.22 0.32 0.05 0.15 0.25 TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE 0.25 0.5 0.75 APPROVAL 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0˚ - 12˚ 27 -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. 530-ASS-P004 VERSION PAGE DWG NO. DATE REALTEK SEMICONDUCTOR, INC. RTL8308B 1 OF Q128 - 1 Oct. 08 1998 Rev. 2.0 ...
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... Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002/01/23 28 RTL8308B Rev. 2.0 ...