EDS6432AFTA-6B-E Elpida Memory, Inc., EDS6432AFTA-6B-E Datasheet

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... SDRAM EDS6432AFTA, EDS6432CFTA Specifications • Density: 64M bits • Organization ⎯ 512K words × 32 bits × 4 banks • Package: 86-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V VDD, VDDQ = 2.5V ± 0.2V • Clock frequency: 166MHz/133MHz (max.) • ...

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... Ordering Information Supply Organization (words × bits) Internal Banks Part number voltage 2M × 32 EDS6432AFTA-6B-E 3.3V EDS6432AFTA-75-E 2M × 32 EDS6432CFTA-75-E 2.5V Part Number Elpida Memory Type D: Monolithic Device Product Family S: SDRAM Density / Bank 64: 64M/4-bank Organization 32: x32 Power Supply, Interface A: 3 ...

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... CONTENTS Specifications ................................................................................................................................................ 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................. 10 Pin Function ................................................................................................................................................ 11 Command Operation................................................................................................................................... 12 Simplified State Diagram ............................................................................................................................ 20 Mode Register Configuration ...................................................................................................................... 21 Power-up Sequence ................................................................................................................................... 23 Operation of the SDRAM ............................................................................................................................ 24 Timing Waveforms ...................................................................................................................................... 40 Package Drawing........................................................................................................................................ 46 Recommended Soldering Conditions ......................................................................................................... 47 Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA 3 ...

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... The supply voltage with all VSS and VSSQ pins must be on the same level. 3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns). 4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns). Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA Symbol Rating VT –0.5 to VDD + 0.5 (≤ 4.6 (max.)) VT – ...

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... Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. Input signals are VIH or VIL fixed. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA EDS6432AF EDS6432CF Grade max. max. ...

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... CI2 Data input/output CI/O capacitance Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition 1MHz, 1.4V(EDS6432AFTA) and 1.2V (EDS6432CFTA) bias, 200mV swing. 3. DQM = VIH to disable DOUT. 4. This parameter is sampled and not 100% tested. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA min. ...

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... Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition 30pF. 3. tLZ (min.) defines the time at which the outputs achieves the low impedance state. 4. tHZ (max.) defines the time at which the outputs achieves the high impedance state. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA -6B -75 Symbol min ...

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... Input and output timing reference levels: 1.2V • Output timing measurement reference level: 1.2V • Input waveform and output load: See following figures 2.1 V 1.7 V input 0.7 V 0.3 V Input waveform and Output load [EDS6432CF] Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA I/O CL ...

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... Register set to active command /CS to command disable Power down exit to command input Notes: 1. lRCD to lRRD are recommended value valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP] Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA -6B -75 166 100 133 Symbol ...

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... Block Diagram CLK Clock Generator CKE Address Mode Register /CS /RAS /CAS /WE Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA Bank 3 Bank 2 Bank 1 Row Address Buffer & Refresh Bank 0 Counter Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & Burst Data Control Circuit ...

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... DQ pins have the same function as I/O pins on a conventional DRAM. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA BA0 ...

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... Table in Pin Function) and the bank select address (BA0, BA1). Write with auto-precharge [WRITA] This command automatically performs a precharge operation after a burst write with a length after a single write operation. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA CKE n – /CS ...

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... BA0 and BA1) at the mode register set cycle. For details, refer to the Mode Register Configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA BA0 L H ...

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... CBR (auto) refresh command Idle Self refresh entry Self refresh Self refresh exit Idle Power down entry Power down Power down exit Remark: H: VIH. L: VIL. ×: VIH or VIL Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA CKE DQM 0 Symbol n – × ENB H L × ...

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... Read Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA /WE Address Command × × DESL × H NOP × L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL × H ...

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... Refresh (auto-refresh Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA /WE Address Command × × DESL × H NOP × L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL × ...

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... NOP for same bank, except for another bank. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. MRS command must be issued after DOUT finished, in case of DOUT remaining. 9. Illegal if lMRD is not satisfied. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA /WE Address Command × × DESL × ...

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... Clock suspend can be entered only from following states, row active, read, read with auto- precharge, write and write with auto precharge. 2. Must be legal command as defined in Function Truth Table. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA /RAS /CAS /WE Address Operation × ...

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... SDRAM enters the IDLE state. Power down exit When this command is executed at the power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA 19 ...

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... POWER POWER APPLIED Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA SELF REFRESH SR ENTRY SR EXIT MRS MODE REFRESH AUTO ...

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... Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA LMODE BT CAS latency A3 Burst type Sequential Interleave Write mode Burst read and burst write ...

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... And the address is increased one by one back to the address 0 when the address reaches at the end of address 255. “Full page burst” stops the burst read/write with burst stop command. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA Burst length = 4 Starting Ad. Addressing(decimal) ...

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... High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device. Power up sequence VDD, VDDQ 0 V Low CKE, DQM Low CLK Low /CS, DQ Power stabilize Power-up sequence and Initialization sequence Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA Initialization sequence 100 μs 200 μs 23 ...

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... Command READ ACT Address Row Column out Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READ out 3 out 0 out 1 out 2 out 0 out 1 out 2 /CAS Latency out 0 out 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 ...

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... CLK Command Address DQ Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA ...

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... CLK ACT Command DQ Note: Internal auto-precharge starts at the timing indicated by " and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READA lRAS out0 out1 out2 READA lRAS out0 out1 " ...

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... CLK Command ACT DQ Note: Internal auto-precharge starts at the timing indicated by " and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA WRITA ACT lRAS in lDAL ". ". Single Write 27 ...

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... During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command. CLK WRITE Command DQ in Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA BST out out out out out Burst Stop at Read ...

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... ACT Address Row 1 Row Bank0 Bank3 Active Active READ to READ Command Interval (different bank) Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READ Column B out A0 out B0 out B1 out B2 out B3 Column =B Column =B Column =A Read Dout Dout When the ROW address changes on same bank, consecutive read ...

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... CLK Command ACT ACT Address Row 1 Row Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA WRIT Column Column =B Write WRIT WRIT Column A Column ...

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... Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READ WRIT ...

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... However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READ out B0 out B1 ...

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... Write A Note: Internal auto-precharge starts at the timing indicated by " Write with Auto Precharge to Write Command Interval (Different bank) 2. Same bank: The consecutive write command (the same bank) is illegal. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA READ out A0 out A1 bank3 Read WRIT ...

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... Write with Auto Precharge to Read Command Interval (Different bank) 2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal necessary to separate the two commands with a bank active command. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA WRIT ...

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... READ to PRECHARGE Command Interval (same bank): To stop output data ( CLK READ PRE/PALL Command DQ READ to PRECHARGE Command Interval (same bank): To stop output data ( Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA PRE/PALL out A0 out A1 out A2 out A3 lEP = -1 cycle PRE/PALL ...

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... A0 WRITE to PRECHARGE Command Interval (same bank) ( (To stop write operation)) CLK Command WRIT DQM WRITE to PRECHARGE Command Interval (same bank) ( (To write all data)) Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA PRE/PALL tDPL PRE/PALL tDPL ...

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... Mode register set to Bank active command interval The interval between setting the mode register and executing a bank active command must be no less than lMRD. CLK Command Address Mode register set to Bank active command interval Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA tRC ACT ACT ROW:0 ROW:1 tRRD ...

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... Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0 clock. CLK DQM DQ CLK DQM DQ Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA High-Z out 0 out 1 lDOD = 2 Latency Reading lDID = 0 Latency Writing ...

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... When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA 39 ...

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... BS tSI tHI tSI A10 tSI tHI tSI Address tSI DQM DQ (input) DQ (output) Bank 0 Bank 0 Read Active Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA t RC tRAS tHI tSI tHI tHI tSI tHI tSI tHI tHI tHI tSI tHI tHI tSI tHI tSI ...

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... CKE /CS /RAS /CAS /WE BS Address code valid DQM DQ (output) DQ (input) lRP Precharge Mode If needed register Set Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA tRC tRAS tSI tHI tSI tSI tHI tSI tSI tSI tHI tSI tHI tSI tSI tSI tHI tSI tSI ...

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... R:a C:a DQM DQ (input) DQ (output) Bank 0 Bank 0 Active Read VIH CKE /CS /RAS /CAS /WE BS R:a C:a Address DQM DQ (input) DQ (output) Bank 0 Bank 0 Active Read Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' High-Z Bank 3 Bank 0 Bank 3 Bank 3 Read Precharge Read ...

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... Bank 0 Active Read Auto Refresh Cycle CLK CKE VIH /CS /RAS /CAS /WE BS Address A10=1 DQM DQ (input) DQ (output Auto Refresh Precharge If needed Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA R:b C: a+1 a+2 a+3 Bank 3 Clock Bank 0 Active suspend Write R:b C:a a a+1 a+2 a+3 a a+1 ...

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... BS Address R:a DQM DQ (output) DQ (input) Bank0 Active clock Active clock Active suspend start supend end Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA lSREX High Self refresh exit Next Self refresh entry ignore command clock command or No operation enable tHI tSI ...

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... CLK CKE VIH /CS /RAS /CAS /WE valid Address VIH DQM DQ tRP All banks Auto Refresh Precharge Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA CKE Low R: a High Power down entry Power down mode exit Active Bank ...

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... A 86 PIN 0.50 0.17 to 0.27 0.10 0.81 max. S 0.10 Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA * 8° Unit: mm 0.80 Nom 0.25 0.50 ± ...

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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDS6432AFTA and EDS6432CFTA. Type of Surface Mount Device EDS6432AFTA, EDS6432CFTA : 86-pin Plastic TSOP(ll) < Lead free (Sn-Bi) > Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA 47 ...

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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA NOTES FOR CMOS DEVICES 48 CME0107 ...

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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E0487E70 (Ver. 7.0) EDS6432AFTA, EDS6432CFTA 49 M01E0107 ...