MB90092PF ETC-unknow, MB90092PF Datasheet
MB90092PF
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MB90092PF Summary of contents
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FUJITSU SEMICONDUCTOR DATA SHEET ASSP for Screen Display Control CMOS ON-Screen Display Controller MB90092 DESCRIPTION The MB90092 is the display controller for displaying text and graphics on the TV screen. The MB90092 incorporates display memory (VRAM), a font memory interface, ...
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MB90092 FEATURES • Main Screen Display • Screen display capacity:24 characters • Character dot configuration:24 • Character types: 16384 different characters (when using bit external clock) • Character sizes: Standard, double width, double height, double width quadruple ...
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External Synchronization Control • Separated sync signal input/composite sync signal input selectable External Interface • 8-bit serial inputs (3 signal input pins) Chip select: CS Serial clock: SCLK Serial data: SIN Package • QFP-80 Miscellaneous • Internal power-on reset ...
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MB90092 PIN ASSIGNMENT TESTI VOC VOB SCLK SIN V CC EXHSYN EXVSYN HSYNC VSYNC VBLNK EXS XS TEST1 FSCO CBCK PDS (TOP VIEW ...
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PIN DESCRIPTION Circuit Pin no. Pin name I/O type 1 TESTI VOC VOB SCLK SIN I ...
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MB90092 Circuit Pin no. Pin name I/O type 17 EXS FSCO CBCK PDS YOUT YIN COUT ...
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Circuit Pin no. Pin name I/O type 44 DA0 45 DA1 46 DA2 47 DA3 DA4 49 DA5 50 DA6 51 DA7 53 ADR0 54 ADR1 55 ADR2 56 ADR3 57 ADR4 58 ADR5 59 ADR6 60 ...
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MB90092 (Continued) Circuit Pin no. Pin name I/O type 19 TEST1 25 TEST2 26 TEST3 O — 27 TEST4 28 TEST5 — — — — ...
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CIRCUIT TYPE Type Circuit MB90092 Remarks CMOS level input With pull-up resistor: approxi- mately 50 k CMOS level, hysteresis input With pull-up resistor: approxi- mately 50 k CMOS output CMOS three state output ...
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MB90092 (Continued EXS Control signal XD EXD I Control signal 10 Control signal Analog input CMOS analog SW Analog input Control signal Analog output CMOS analog SW Analog output Control signal CMOS level, hysteresis input ...
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BLOCK DIAGRAM SIN Serial input SCLK CS control TEST VIN YIN CIN VKIN H/V separation EXHSYN EXVSYN circuit NTSC/PAL HSYNC signal VSYNC generator VBLNK Display memory control Display memory VRAM ( 4FSC clock XS EXS oscillator XD Dot clock EXD ...
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MB90092 DISPLAY CONTROL COMMANDS Command Function no. 0 10000 VSL RA8 RA7 VRAM address setting Main screen 1-1 character control 10001 MA data setting 1* Main screen 2-1 10010 character control data setting 2 Sub-screen line 1-2 10001 SMA SMB ...
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COMMAND 1. VRAM Address Setting (Command 0) MSB First byte 1 0 MSB Second byte 0 RA6 VSL : VRAM write control RA8 to RA5 : VRAM row address setting (0 CA4 to CA0 : VRAM column address setting (00 ...
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MB90092 (2) Writing sub-screen line control data (when command 0: VSL = 1, CA0 = 0) Command 1-2 (Sub-screen line control data setting 1) MSB First byte 1 MSB Second byte SCG 0 Command 2-2 (Sub-screen line control data setting ...
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Writing main screen control data (when command 0: VSL = 1, CA0 = 1) Command 1-3 (Main screen line control data setting 1) MSB First byte 1 0 MSB Second byte 0 0 Command 2-3 (Main screen line control ...
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MB90092 4. Screen Control 1 (Command 4) MSB First byte 1 MSB Second byte Internal/external synchronization control IN : Interlaced/noninterlaced display control EB : Screen background display control EO : Field control CM : Color/monochrome display control ...
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Main Screen Line Control (Command 6) MSB First byte 1 MSB Second byte 0 SOC SOC Main Screen Vertical Display Position Control (Command 7) MSB First byte 1 0 MSB ...
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MB90092 9. Main Screen Display Mode Control (Command 9) MSB First byte 1 MSB Second byte 0 GRM: Main screen display mode control RP1, RPO : Reserve 4* S16 SF1 DW4 RM1, RM0 : Reserve 0* *: Reserve 0 to ...
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Sub-Screen Control (Command 11) MSB First byte 1 MSB Second byte 0 SG2 to SG0 SCC SBC SGC SBG, SBR, SBB : Sub-screen pattern background color 12. Sub-Screen Vertical Display Position Control (Command 12) MSB First byte 1 MSB ...
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MB90092 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature *1: AV and V must have equal potential *2: Neither V nor V must exceed “V IN OUT WARNING: Semiconductor devices ...
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ELECTRICAL CHARACTERISTICS 1. DC Characteristics Sym- Parameter Pin bol “H” level VOC, VOB, B, output HSYNC, OH voltage VSYNC, VBLNK, FSCO, “L” level READ, output V OL ADR0 to ADR20 voltage TESTI, CS, SCLK, SIN, EXHSYN, Input ...
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MB90092 Sym- Parameter Pin bol Yellow V YELH High level Yellow V YELL Low level Cyan V CYAH High level Cyan V CYAL Low level Green V GREH High level Green V GREL Low level Magenta V MAGH High level ...
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Sym- Parameter Pin bol White level 3 V WHT3 = – 270 Y WHT3 White level 2 V WHT2 = – 180 Y WHT2 White level 1 V WHT1 = – WHT1 White level 0 V WHT0 = ...
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MB90092 (Continued) Sym- Parameter Pin bol Yellow C YELH High level Yellow C YELL Low level Cyan C CYAH High level Cyan C CYAL Low level Green C GREH High level Green C GREL Low level Magenta C MAGH High ...
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VOUT Output V WHT0 3 V GRY6 V GRY5 V GRY4 V BSTH V PDS V BSTL V TIP • YOUT Output Y WHT0 3 Y GRY6 Y GRY5 Y GRY4 Y PDS Y TIP • COUT Output C ...
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MB90092 2. AC Characteristics Parameter Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select end time Chip select signal rise/fall time Horizontal sync signal ...
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Serial Input Timings 0 0 CFC SCLK t WCH t CR SIN • Vertical and Horizontal Sync Signal Input Timings EXHSYN EXVSYN t CYC t WCL ...
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MB90092 • Composite Sync Signal Input Timings EXHSYN t HF EXHSYN EXHSYN • Reset Signal Input Timing TESTI 28 0 0 WCSH HR 0 ...
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Address Data Hold Timings EXD ADR0 Main screen data address * to ADR20 READ DA0 to Main screen data * DA7 • Address and READ Signal Delays at TSC Signal Input ADR0 to ADR20 READ TSC ...
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MB90092 3. Clock Timing Specifications Parameter Symbol Display dot clock* Color burst clock (NTSC)* Color burst clock (PAL Input the signal with a duty cycle of 50%. 4. Power-on Reset Specifications Parameter Power-supply rise time Power-supply off time ...
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Power ON/OFF Timing 4 Note: The power supply must be activated smoothly. • Power-on Reset Cancel Timing V CC Internal reset off 4 WIT t ...
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MB90092 5. Recommended Input Timings (1) Composite sync signal input timing Parameter Number of frame scan lines Field frequency Line frequency Vertical retrace blanking interval First equalizing pulse interval Vertical sync pulse interval Second equalizing pulse interval Equalizing pulse width ...
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Output Timings (1) Horizontal timing Symbol NTSC HPS 0 EQP1E 34 HPE 68 BSTS 76 BSTE 112 HBLKE 143 SEP1S 388 EQP2S 455 EQP2E 489 SEP2S 842 HBLKS 888 IHCLR 910 *: Parenthesized values assume the last raster in ...
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MB90092 • NTSC/PAL Horizontal Timings Video signal Horizontal sync signal Horizontal retrace blanking interval Burst flag Equalizing pulse Cut-in pulse 34 EQP2E IHCLR EQP2S HBLKS SEP1S SEP2S HBLKE BSTE BSTS HPE EQP1E HPS HBLKS ...
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NTSC Vertical Timings MB90092 35 ...
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MB90092 • PAL Vertical Timings 36 ...
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SAMPLE CIRCUIT This is a standard example of the circuit to synthesize the character to input video signal or input internal generation video signal from the outside. Note that composition is different according to the system and parts used. Composite ...
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... MB90092 ORDERING INFORMATION Part number MB90092PF 38 Package 80-pin, plastic QFP (QFP-80P-M06) Remarks ...
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PACKAGE DIMENSION 80-pin plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 20.00±0.20(.787±.008 INDEX 80 1 0.80(.031) 0.37±0.05 (.015±.002) "A" 2001 FUJITSU LIMITED F80010S-c-4-4 C Note : Pins width and pins thickness include plating thickness 0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) Details ...
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MB90092 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North ...