ACD82224 ETC-unknow, ACD82224 Datasheet
ACD82224
Available stocks
Related parts for ACD82224
ACD82224 Summary of contents
Page 1
... Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD’ s website for update information before starting a design Web site: http://www.acdcorp.com Email: support@acdcorp.com ACD Confidential Material Use under Non-Disclosure Agreement only. No reproduction or redistribution without ACD’s prior permission. ...
Page 2
CONTENT LIST 1. GENERAL DESCRIPTION ............................................................................................................. 3 2. MAJOR FEATURES........................................................................................................................ 5 3. SYSTEM BLOCK DIAGRAM......................................................................................................... 5 4. SYSTEM DESCRIPTION................................................................................................................ 6 MACs, RMII & MII Interfaces ......................................................................................................... 6 Queue Manager ................................................................................................................................ 6 Built-in ARL & External-ARL Interface.......................................................................................... 6 Register & UART ...
Page 3
SYSERR register (register 2) .......................................................................................................... 29 PAR register (register 3)................................................................................................................. 29 PMERR register (register 4) ........................................................................................................... 29 ACT register (register 5)................................................................................................................. 29 SAL & SAH register (register 8,9).................................................................................................. 30 UTH register (register 10)............................................................................................................... 30 BTH register (register 11)............................................................................................................... 31 MINL ...
Page 4
... GENERAL DESCRIPTION The ACD82224 is a single chip implementation of 24-port 10/100 Ethernet switch system intended for IEEE 802.3 and 802.3u compatible networks. The device includes 24 independent 10/100 MACs. Each MAC interfaces with an external PMD/PHY device through a Reduced MII (RMII) interface. The last port is RMII and MII selectable. When in MII mode, this port becomes a shared port with the in-band management CPU ...
Page 5
... Figure-1.2: ACD82224 Based 24 Ports 3-Chip Managed 10/100 Switch System MAG 22-20 Quad RMII PHYs RMII Bus ACD80900 DRAM Flash Crystal CPU RS-232 Transceiver Serial Interface Page MAG MAG 19-16 15-12 Quad Quad RMII RMII PHYs PHYs 4 RMII 4 RMII Bus 4 RMII Bus Bus 3 RMII ...
Page 6
... PMD/ MAC-1 PHY-1 FIFO FIFO PMD/ MAC- PHY- (xx-2) (xx-2) FIFO FIFO PMD/ MAC- PHY- (xx-1) (xx-1) FIFO xx=16 for ACD82216 24 for ACD82224 Page compatible SRAM at 100MHz ACD822xx Buffer Lookup Engine Buffer (2K MAC Addr.) Buffer Buffer MX DMX Buffer Buffer Buffer ARL Interface Buffer ARL ACD80800 (11K MAC Addr ...
Page 7
... Through the serial CPU interface of the ACD82224 switch, a management CPU can learn the address change in the lookup table. Hence, the ACD82224 alone can be used to build a complete Fast Ethernet switch with up to 2,048 host connections. (See Appendix-A for detail) For workgroup or backbone switches, the ACD82224 can support more MAC addresses per port through the use of an external ARL chip, the ACD80800 ...
Page 8
... Register & UART Interface A System CPU can access various registers inside the ACD82224 through a serial CPU management interface (UART). The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers within the ACD82224 switch ...
Page 9
... VLAN, except the source port itself. SA (Source Address 48-bit field that contains the MAC address of the source DTE that is transmitting the frame to the ACD82224. After a frame is received with no error, the SA is learned as the port’s MAC address. Type/Len field is a 2-byte field that specifies the type (DIX Ethernet frame) or length (IEEE 802 ...
Page 10
... Under normal operating conditions, the ACD82224 expects a received frame to have a minimum inter frame gap (IFG). The minimum IFG required by the ACD82224 packet comes with an IFG less than 64 BT, the ACD82224 will not guarantee the reception of that frame. The packet may be dropped not properly received. ...
Page 11
... Any frame heading to its own source port will be filtered. When external ARL is used, the filtering decision will be made by the ARL. The ACD82224 will act in accordance with the ARL’s decision. If the Spanning Tree Support option (Bit 1 of Register 16) is set, a frame with DA equal to 01-80- C2-00-00-00 will be forwarded to port-23 (the default CPU port BPDU frame ...
Page 12
... Shared Buffer All ports of the ACD82224 work in Store-And-Forward mode so that all ports can support both 10Mbps and 100Mbps data speeds. The ACD82224 utilizes a global memory buffer pool, which is shared by all ports. The device has a unique architecture that inherits the advantages of both ...
Page 13
... Starvation Control Scheme All frames received by the ACD82224 will be stored into a common physical frame buffer pool. In order to make sure all ports have fair access to the network, a buffer allocation scheme (starvation control) is used to prevent active ports from occupying all the buffers and starving off the less active ports ...
Page 14
... Frame is sent, and if the broadcast queue is below the “Lower Threshold” in Register-11, a Mini- Pause-Frame will be sent to release the hold on transmission. Port-based VLAN Support (Registers 23 & 24) The ACD82224 can support port-based security VLANs. Each port of the ACD82224 can be assigned four VLAN. On power up, every port is assigned to VLAN-I as the default Page ...
Page 15
... That is, the dumping port can be used to connect the switch with a computer repeater hub, a workgroup switch, a router, or any type of interconnection device compliant with IEEE 802.3 standard. ACD82224 will direct the following frames to the dumping port: (1) A frame with unknown unicast destination address. ...
Page 16
... PHY capability field like Link, Speed, and Duplex status to ensure proper operation of the link. The ACD82224 also enables the CPU to access any registers in the PHY devices through the CPU interface (See Register-32 example). The ID of the PHY device can start from either “0” or “ ...
Page 17
... CPU. ACD82224 also allows the CPU to access any registers in the PHY devices through the CPU interface. SRAM Interface The ACD82224 uses pipeline ZBT speed should be 100MHz or faster. Each read or write cycle should take no more than 10 ns. The SRAM interface contains a 52-bit data bus (48-bit data and 4-bit status), a 19-bit address bus, and 2 control signals ...
Page 18
... LED signals, refer to the chapter of “Timing Description ” Life Pulse The ACD82224 will generate Life Pulses at WCHDOG pin once every 800 nsec to indicate normal operation status. Absence of the Life Pulses is an indication that, the ACD82224 has encountered some fatal error and needs to be reset. The life pulses are used to reset a watchdog counter, such that, if the watchdog counter is not reset and has reached a predetermined value, a system reset signal can be generated to reset the ACD82224 ...
Page 19
... INTERFACE DESCRIPTION Figure-6.1 shows all the interfaces of the ACD82224 controller and their relations to other modules in a typical switch system. Table-6.1 list all function pins grouped by types. Figure-6.1 Major Interface Group P(a) RMII P(a+1) RMII * a=8 for 82216 RMII 0 for 82224 PHY P23 RMII RMIICLK[0:5] ...
Page 20
... RMIICLK. The detailed timing requirement is described in the chapter of “Timing Description” MII Interface (MII) The last port (e.g. Port-23 on the ACD82224) can be selected to act in MII mode. The MII mode is used to connect the ACD80900 for in-band management function. The ACD80900 acts as a three-way switch to allow the management CPU to share the regular port. The signals of MII interface are described in Table-6 ...
Page 21
... After the completion of the write transaction, the line will be left in a high impedance state. For a read operation, the ACD82224 will output a ‘10’ to indicate read operation after the start of frame indicator. Following the ‘10’ read signal will be the 5-bit ID address of the PHY device and the 5-bit register address ...
Page 22
... Command octet. CPUIRQ is high active and used to notify the CPU that some special status has been encountered by the ACD82224, like port partition, and fatal system error, etc. By clearing the appropriate bit in the interrupt mask register, the specific source interrupt can be stop. Reading the interrupt source register retrieves the source of the interrupt request and clears the interrupt source register ...
Page 23
... ACD80900 collect traffic information by monitoring the data bus of the buffer memory. The two interfaces share many common pins, as shown in Figure-6.1and Table-6.9. When the ACD82224 receives a frame, it will store it into the frame buffer memory through data bus DATA[47:0]. The external ARL extracts the destination address and source address of the frame posted on the Data [0:47] while it is written into the memory ...
Page 24
Table-6.9: ARL & MIB Interfaces Signals Name Type DATA[47:0] O Frame Data BE[2:0] O Byte Enable: BE[0:2] EOF O End of Frame: EOF SWDIR[1:0] O Data Direction Indicator : 00 = idle receive transmit ...
Page 25
LEDCLK, and should be sampled by the rising edge of LEDCLK. LED data of port-23 are clocked out first, followed by port-22 down to port-0. All LED signals are low active. The signals in the LED interface ...
Page 26
Configuration Interface The default values of certain register bits are set by internal pull-high/pull-low 75K Ohm resistors. These default values can be overwritten by external pull-high/pull-low with 4.7K Ohm resistors. Table-6.11 lists all the available pins. The meanings of the ...
Page 27
... The CLK100 should come from 100MHz clock oscillator, with 3.3Volt or 5Volt, 40/60 Duty Cycle, and 50 ppm accuracy. The nRESET is a low-active hardware reset pin. Assertion of this pin will cause the ACD82224 to go through a power-up initialization process. All registers are set to their default value after reset. ...
Page 28
... REGISTER DESCRIPTION Registers in the ACD82224 are used to define the operational mode of various function modules of the switch controller and the peripheral devices. Default values at power-on are predefined. The management CPU (optional) can read the content of all registers and modify some of the registers to change the operational mode. Table-7.0.1 lists all the registers inside the switch controller ...
Page 29
... System initialization completed 1 System error occurred 2 Port partition occurred 3 ARL Interrupt Note: The source interrupt for bit-3 ARL interrupt is referred to ARL Register-13. Page Port Number ACD82224 0 Port 0 1 Port 1 2 Port 2 3 Port 3 4 Port 4 5 Port 5 6 Port 6 ...
Page 30
SYSERR register (register 2) The SYSERR register indicates the presence of system errors automatically cleared after each read. Table-7.2 lists the system error reported. Table-7.2: SYSERR Register Bit PAR ...
Page 31
SAL & SAH register (register 8,9) The SAL and SAH registers together contain the complete Source Address for pause frame generation. SAL contains the least significant 24 bit of the MAC address. SAH contains the most significant 24 bit of ...
Page 32
BTH register (register 11) The BTH register contains the broadcast queue buffer threshold for each port. When the upper threshold is exceeded, the MAC may generate a Max-Pause-Frame. When the lower threshold is crossed, the MAC may generate a Mini-Pause-Frame. ...
Page 33
... Port 23 is MII 1 – Port 23 is RMII (POS shared with P03TXEN) If the bit-19 of Register-25 is set (CPU start mode), ACD82224 will stop the initialized procedures after it is completed with self-test. CPU must set bit-5 of register-16 to enable access internal registers. CPU set bit-6 of register-16 to enable MAC and Queue manager. Then ACD82224 will start switching based on CPU’ ...
Page 34
... These two modes are also applied to the SPEED (register-18), LINK (register-19), DPLX (register-27), PAUSE (register-26) register. (1) Automatic PHY management mode (default setting): These four registers controlled by ACD82224's PHY management Hardware update their status. To enable this mode if bit-16 of register-25 is cleared, and the corresponding bit (port) in nPM register (register-29) is cleared. ...
Page 35
The nFWD register defines the forwarding mode of each port. Under forwarding mode, a port can forward all frames. Under block-and-listen mode, a port will not forward regular frames, except BPDU frames. If the spanning tree ...
Page 36
PVID register (register 23) The PVID registers assign VLAN IDs for each port. There are 24 PVID registers, one for each port. A PVID consists of 4 bits, each corresponding bit mapping to one of the 4 VLANs. A port ...
Page 37
Table-7.25: POSCFG Register Bit Description 3:0 ZBT SRAM Read Timing Adjustment (16 levels within clock cycle, each delay unit adds approximately 0.5-0.7 ns, “inversion” adds one half of clock cycle to the delay) 0001 ...
Page 38
PAUSE register (register 26) The PAUSE register defines the pause-frame based flow control capability of each port. Table- 7.26 describes all the bits of this register. Table-7.26: PAUSE Register Bit [0:23] 0 – Port X Pause-Frame disabled 1 – Port ...
Page 39
... PHYREG register (register 32-63) The PHYREG refers to the registers residing on the PHY devices. The ACD82224 provides a mirror access path for the control of CPU to access the registers on the PHYs. For detailed information about the PHY registers, please refer to the PHY data sheet. The register index is used by the ACD82224 to specify the PHY's internal registers ...
Page 40
PIN DESCRIPTIONS Figure-8.1: Pin Diagram/Bottom View AF AE Page Confidential ...
Page 41
RMII Clock Interface Pin Name Location RMIICLK0 AC07 RMIICLK1 AF16 RMIICLK2 AE24 RMIICLK3 V24 RMIICLK4 J25 RMIICLK5 C23 RMII Interface (Port 0 ~ Port 22) Pin Name Location P00CRS_DV AE10 P00RXD0 AF10 P00RXD1 AC10 P00TXD0 AC09 P00TXD1 AD08 P00TXEN AD07 ...
Page 42
P05TXD1 AF19 P05TXEN AF18 P06CRS_DV AF21 P06RXD0 AD20 P06RXD1 AE22 P06TXD0 AD19 P06TXD1 AE21 P06TXEN AF20 P07CRS_DV AC22 P07RXD0 AF23 P07RXD1 AD22 P07TXD0 AD21 P07TXD1 AE23 P07TXEN AF22 P08CRS_DV AD25 P08RXD0 AD26 P08RXD1 AC25 P08TXD0 AF24 P08TXD1 AE26 P08TXEN AD23 ...
Page 43
... A24 P19RXD1 B23 P19TXD0 C26 P19TXD1 A25 Page POS REG Bit-20: 2-bit device ID bit-0 for UART communication. ACD82224 responses only to UART commands with matching ID. I Carrier Sense/Receive data valid I Receive data bit 0 I Receive data bit 1 O Transmit data bit 0 ...
Page 44
P19TXEN D24 P20CRS_DV A22 P20RXD0 B21 P20RXD1 C21 P20TXD0 B22 P20TXD1 D22 P20TXEN A23 P21CRS_DV C20 P21RXD0 D18 P21RXD1 A19 P21TXD0 B20 P21TXD1 A20 P21TXEN A21 P22CRS_DV B17 P22RXD0 C18 P22RXD1 A17 P22TXD0 B18 P22TXD1 A18 P22TXEN C19 MII Interface ...
Page 45
MDIO AC03 CPU Interface Signals Name Type UARTDI U03 UARTDO T03 SWIRQ C06 ZBT SRAM Interface Pin Name Location DATA00 F01 DATA01 F02 DATA02 G01 DATA03 G02 DATA04 H01 DATA05 H02 DATA06 J01 DATA07 J02 DATA08 K01 DATA09 K02 DATA10 ...
Page 46
AF07 BE00 AF08 BE01 AE08 BE02 AF09 EOF AE07 Page I/O Byte enable I/O Byte enable I/O Byte enable I/O End of frame Confidential Page 45 45 ...
Page 47
ADDR00 B03 ADDR01 B01 ADDR02 C02 ADDR03 C01 ADDR04 D02 ADDR05 D01 ADDR06 E01 ADDR07 E02 ADDR08 B07 ADDR09 A07 ADDR10 A03 ADDR11 B04 ADDR12 A04 ADDR13 B05 ADDR14 A05 ADDR15 B06 ADDR16 A06 ADDR17 B08 ADDR18 A08 C04 nWE ...
Page 48
ARLDI02 H03 ARLDI03 K04 ARLDIV J04 LED Interface Signals Pin Name Location LEDVLD0 W03 LEDVLD1 Y04 LEDCLK V03 nLED0 R04 nLED1 R03 nLED2 N03 nLED3 P04 System Control interface Signals Pin Name Location CLK100 AB04 WCHDOG Y03 SYSERROR M03 nRESET ...
Page 49
Table-8.1a: Pin List Sorted by Location ( Location Pin Name I/O POS Location A01 VSS A02 VSS A03 ADDR10 O A04 ADDR12 O A05 ADDR14 O A06 ADDR16 O A07 ADDR09 O A08 ADDR18 O A09 ...
Page 50
Location Pin Name I/O H03 ARLDI2 I H04 VSS H23 P16RXD0 I H24 P17TXEN I/O H25 VDDQ H26 P16TXD0 O J01 DATA06 I/O J02 DATA07 I/O J03 VDDQ J04 ARLDIV I J23 VSS J24 P16TXD1 O J25 MIICLK4 O J26 ...
Page 51
Table-8.1c: Pin List Sorted by Location ( Location Pin Name I/O Y01 DATA28 I/O Y02 DATA29 I/O Y03 WCHDOG O Y04 LEDVLD1 I/O Y23 P09RXD1 I Y24 P10RXD0 I Y25 P10TXD1 O Y26 P10CRS_DV I AA01 ...
Page 52
Table-8.2a: Pin List Sorted by Name ( Pin Name I/O POS Location ADDR00 O B03 ADDR01 O B01 ADDR02 O C02 ADDR03 O C01 ADDR04 O D02 ADDR05 O D01 ADDR06 O E01 ADDR07 O E02 ...
Page 53
Table-8.2b: Pin List Sorted by Name ( Pin Name I/O POS Location P05TXD0 I/O 39 AE19 P05TXD1 I/O 40 AF19 P05TXEN I/O 29 AF18 P06CRS_DV I AF21 P06RXD0 I AD20 P06RXD1 I AE22 P06TXD0 O AD19 ...
Page 54
Table-8.2c: Pin List Sorted by Name ( Pin Name I/O POS Location SWIRQ O C06 SWRXCLK O A09 SWSYNC O E03 SWTXCLK O A11 SYSERR O M03 TESTEN I D07 UARTDI I U03 UARTDO O T03 ...
Page 55
TIMING DESCRIPTION RFE_CLK RXD[1: RXDV, RXD setup time t2 RXDV, RXD hold time Figure-9.1a RMII Receive Timing Figure-9.1b: RMII Transmit Timing REF_CLK TXD[1:0] Page Description: MIN TYP ...
Page 56
Figure-9.2a MII Receive Timing RXCLK RXDV RXD[3:0] RXER T# t1 RX_DV, RXD, RX_ER setup time t2 RX_DV, RXD, RX_ER hold time Figure-9.2b: MII Transmit Timing TXCLK TXEN TXD[3:0] Page Description: MIN TYP ...
Page 57
Figure-9.3: PHY Management Read Timing t2 MDC MDIO Figure-9.4: PHY Management Write Timing MDC MDIO Page Description MIN TYP MAX UNIT MDIO setup time 0 - 300 ns MDC cycle - 800 - ...
Page 58
Figure-9.5: SRAM (ZBT) Read/Write Timing MCLK nCE nWE ADDRESS DATA t10 t11 t12 t13 t14 t15 Page ...
Page 59
Figure-9.6: CPU Command Timing t1 idle state CPUDI bit bit stop CPUDO 6 7 bit Figure-9.7: ARL Result Timing ARLCLK ARLDO DA1 ARLDI Page start bit 0 bit 1 bit 2 bit 3 bit 4 ...
Page 60
Figure-9.8: LED Signal Timing LEDCLK LEDVLD0 LEDVLD1 nLED0 nLED1 nLED2 nLED3 LNK LNK LNK P22 P23 P21 * P[7:0] time slots is not used for 82216 Page 59 ...
Page 61
ELECTRICAL SPECIFICATION 10. ELECTRICAL SPECIFICATION Figure-10.1: Absolute Maximum Ratings Item DC supply voltage for Core DC supply voltage for I/O Input signal voltage Signal current DC output voltage Figure-10.2 Recommended Operation Conditions Item DC supply voltage for Core DC ...
Page 62
PACKAGING 0.56 Page Top View 35 30 Advanced Comm. Devices FLLLLL SMAYYWW ACD822xx Side View Bottom View 1.27 0.635 0.75 Confidential 2.33 0.6 Page 61 61 ...
Page 63
Address Resolution Logic Built-in ARL with 2048 MAC Addresses Page Appendix-A1 Confidential Page 62 62 ...
Page 64
SUMMARY The internal Address Resolution Logic (ARL) of the switch controllers automatically builds up an address table and maps up to 2,048 MAC addresses for the associated ports. CPU intervention is not required in an UN-managed system. For a ...
Page 65
FEATURES Supports up to 2,048 internal MAC address lookup Provides UART type of interface for management CPU Wire speed address lookup time. Wire speed address learning time. Address can be automatically learned from switch without external CPU intervention Address ...
Page 66
The default aging time is 300 seconds. That means Address Aging Engine checks the timer every 300 seconds from power up. If the new address is learned just after the aging-out checking process finished. The worst case aging time can ...
Page 67
... The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the Command octet. For each valid command received, the ARL will always send a response. Response from the ARL is sent through the CPUDO line. Response frames sent by the ACD82224 have the following format: ARL UARTDO (Response) Format ...
Page 68
Read 0100XX01 For response to a read operation, the Data field is a 4-octet value to indicate the content of the register. For response to a write operation, the Data field is 32 bits the data of ...
Page 69
DataReg0 ~ DataReg7 (Register 0 ~ Register 7) The DataReg[0:7] are registers used to pass the command parameters to the ARL, and the ARL only stores 47-bit of MAC address, the first bit of the execution results to the CPU. ...
Page 70
RstReg (Register 11) The RstReg is used to indicate the status of command execution. The result code is listed as follows: Bit 3:0 4-bit error code 0000 – No error 0001 – Cannot find the specified entry Other – Errors ...
Page 71
Aged address exists 1 New address exists 2 Reserved 3 Reserved 4 Bucket overflowed 5 Command is done 6 System initialization is completed 7 Self test failure nLearnReg0 ~ nLearnReg2 (Register 15 ~ Register 17) The nLearnReg[2:0] are used ...
Page 72
Parameter: Store the MAC address into DataReg5 – DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the associated port number into DataReg6. Result: the MAC address will be stored into the address ...
Page 73
DataReg5 – DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7.The Read Pointer will ...
Page 74
MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 30H Description: ...
Page 75
Command 31H Description: Read next new entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next new entry from the Read Pointer of the address book ...
Page 76
Command 51H Description: Read next locked entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next locked entry from the Read Pointer of the address book ...
Page 77
Command 81H Description: Read next valid entry. Parameter: Store port number into DataReg6. Result: The result is indicated by the Result register. If the command is completed with no error, the content of next entry from the Read Pointer of ...