EDS1216AATA-75-E Elpida Memory, Inc., EDS1216AATA-75-E Datasheet
EDS1216AATA-75-E
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EDS1216AATA-75-E Summary of contents
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... SDRAM EDS1216AATA (8M words 16 bits) Description Features DATA SHEET Pin Configurations 54-pin Plastic TSOP (II) 1 VDD 2 DQ0 3 VDDQ 4 DQ1 5 DQ2 6 VSSQ 7 DQ3 8 DQ4 9 VDDQ 10 DQ5 11 DQ6 12 VSSQ 13 DQ7 14 VDD 15 LDQM 16 /WE 17 /CAS 18 /RAS 19 /CS 20 BA0 21 BA1 22 A10 ...
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... Ordering Information Part Number Elpida Memory Type D: Monolithic Device Product Family S: SDRAM Density / Bank 12: 128M/4-bank Organization 16: x16 Power Supply, Interface A: 3.3V, LVTTL Die Rev. EDS1216AATA Environment Code E: Lead Free Speed 75: 133MHz/CL3 100MHz/CL2 Package TA: TSOP (II) ...
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... CONTENTS EDS1216AATA ...
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... Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions ( + EDS1216AATA ...
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... DC Characteristics 1 ( +70 C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) EDS1216AATA ...
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... DC Characteristics 2 ( +70 C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V) EDS1216AATA ...
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... EDS1216AATA Unit Notes ...
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... Test Conditions 2.4 V 2.0 V input 0.8 V 0 Input waveform and Output load EDS1216AATA CL ...
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... Relationship Between Frequency and Minimum Latency EDS1216AATA ...
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... Block Diagram CLK Clock Generator CKE Address Mode Register /CS /RAS /CAS /WE Bank 3 Bank 2 Bank 1 Row Address Buffer & Refresh Bank 0 Counter Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & Burst Data Control Circuit Counter EDS1216AATA UDQM and LDQM DQ ...
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... CLK (input pin) CKE (input pins) /CS (input pins) /RAS, /CAS, and /WE (input pins A11 (input pins) BA0 and BA1 (input pin) [Bank Select Signal Table] UDQM and LDQM (input pins) DQ0 to DQ15 (input/output pins) VDD, VSS, VDDQ, VSSQ (Power supply) EDS1216AATA ...
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... Command Operation Command Truth Table Device deselect command [DESL] No operation [NOP] Burst stop command [BST] Column address strobe and read command [READ] Read with auto-precharge [READA] Column address strobe and write command [WRIT] Write with auto-precharge [WRITA] EDS1216AATA ...
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... Row address strobe and bank activate [ACT] Precharge selected bank [PRE] [Bank Select Signal Table] Precharge all banks [PALL] Refresh [REF/SELF] Mode register set [MRS] EDS1216AATA ...
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... DQM Truth Table l l CKE Truth Table EDS1216AATA ...
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... Function Truth Table EDS1216AATA ...
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... EDS1216AATA ...
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... EDS1216AATA ...
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... Command Truth Table for CKE EDS1216AATA ...
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... Clock suspend mode entry ACTIVE clock suspend READ suspend and READ with Auto-precharge suspend WRITE suspend and WRIT with Auto-precharge suspend Clock suspend Clock suspend mode exit IDLE Auto-refresh command [REF] Self-refresh entry [SELF] Power down mode entry Self-refresh exit Power down exit EDS1216AATA ...
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... CLOCK SUSPEND CKE_ CKE ROW ACTIVE BST WRITE READ WRITE READ Read WITH WITH AP AP CKE_ READ WRITE READ WRITE CKE READ WRITE WITH AP WITH AP READ WITH AP PRECHARGE CKE_ WRITEA READA CKE PRECHARGE PRECHARGE PRECHARGE PRECHARGE EDS1216AATA READ SUSPEND READA SUSPEND ...
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... R 1 Interleave Write mode Burst read and burst write R Burst read and single write F.P.: Full Page R is Reserved (inhibit Mode Register Set EDS1216AATA Burst length BT=0 BT ...
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... Burst Sequence EDS1216AATA Burst length = 4 Starting Ad. Addressing(decimal Sequential Interleave ...
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... Power-up sequence Power-up sequence Initialization sequence Power up sequence VDD, VDDQ 0 V CKE, Low UDQM, LDQM Low CLK Low /CS, DQ Power stabilize Power-up sequence and Initialization sequence Initialization sequence 100 s 200 s EDS1216AATA ...
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... out 0 out out 0 out 1 out 2 out out 0 out 1 out 2 out out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 /CAS Latency out 4 out 5 out 6 out 7 Burst Length EDS1216AATA CL = /CAS latency Burst Length = Burst Length /CAS Latency = 2 ...
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... Command ACT WRIT Address Row Column CLK Command Address Row Burst write tRCD ACT WRIT Column in 0 Single write EDS1216AATA ...
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... READA lRAS out0 out1 out2 READA lRAS out0 out1 ". ". Burst Read ( WRITA lRAS in0 in1 in2 in3 lDAL ". ". Burst Write ( EDS1216AATA l ACT out3 lAPR ACT out2 out3 lAPR l ACT ...
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... CLK Command ACT lRAS DQ Note: Internal auto-precharge starts at the timing indicated by " and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ". Single Write EDS1216AATA WRITA ACT in lDAL ". ...
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... Burst Stop Command CLK READ Command CLK WRITE Command DQ in BST out out out out out Burst Stop at Read Burst Stop at Write EDS1216AATA High-Z High-Z out BST High-Z ...
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... Bank0 Bank3 Bank0 Active Active Read READ to READ Command Interval (different bank) out A0 out B0 out B1 out B2 out B3 Column =A Column =B Dout Read Dout READ Column B out A0 out B0 out B1 out B2 out B3 Bank0 Bank3 Bank3 Dout Dout Read EDS1216AATA Bank ...
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... ACT WRIT Address Row 1 Column A Row Bank0 Bank3 Bank0 Active Active Write WRITE to WRITE Command Interval (different bank Write WRIT Column Bank3 Write EDS1216AATA Burst Write Mode Bank 0 Burst Write Mode ...
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... CLK Command CL=2 UDQM LDQM CL=3 DQ (input) DQ (output) READ to WRITE Command Interval (1) CLK Command UDQM LDQM CL=2 DQ CL=3 READ to WRITE Command Interval (2) READ WRIT High-Z READ WRIT 2 clock out out out in in out out in in EDS1216AATA Burst write ...
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... A1 DQ (output) Column = A Write WRITE to READ Command Interval (2) READ out B0 out B1 /CAS Latency Column = B Dout READ out B0 out B1 /CAS Latency Column = B Column = B Read Dout EDS1216AATA out B2 out B3 Burst Write Mode Bank 0 out B2 out B3 Burst Write Mode Bank 0 ...
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... bank0 Write A Note: Internal auto-precharge starts at the timing indicated by " Write with Auto Precharge to Write Command Interval (Different bank) READ out A0 out A1 out B0 bank3 Read ". WRIT bank3 Write ". EDS1216AATA out B1 CL BL= 4 ...
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... A0 DQ (output) bank0 bank3 WriteA Read Note: Internal auto-precharge starts at the timing indicated by " Write with Auto Precharge to Read Command Interval (Different bank) WRIT High-Z bank3 Write out B0 out B1 EDS1216AATA ". out B2 out ". ...
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... READ to PRECHARGE Command Interval (same bank): To stop output data ( CLK PRE/PALL READ Command DQ READ to PRECHARGE Command Interval (same bank): To stop output data ( PRE/PALL out A0 out A1 out A2 out A3 lEP = -1 cycle PRE/PALL out A0 out A1 out A2 CL=3 lEP = -2 cycle High-Z out A0 lHZP = 2 High-Z out A0 lHZP =3 EDS1216AATA l out A3 ...
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... WRIT Command UDQM LDQM WRITE to PRECHARGE Command Interval (same bank) ( (To stop write operation)) CLK Command WRIT UDQM LDQM WRITE to PRECHARGE Command Interval (same bank) ( (To write all data)) PRE/PALL in A2 tDPL PRE/PALL tDPL EDS1216AATA ...
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... Mode register set to Bank active command interval CLK Command Address Mode register set to Bank active command interval tRC ACT ACT ROW:1 tRRD Bank 3 Active Active MRS ACT OPCODE BS & ROW lMRD Mode Bank Register Set Active EDS1216AATA ACT ROW Bank 0 Active l ...
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... DQM Control Reading Writing CLK UDQM LDQM DQ CLK UDQM LDQM DQ High-Z out 0 out 1 out 3 lDOD = 2 Latency Reading lDID = 0 Latency Writing EDS1216AATA in 3 ...
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... Refresh Auto-refresh Self-refresh Others Power-down mode Clock suspend mode EDS1216AATA ...
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... AC tOH tOH tOH tOH tLZ Bank 0 Precharge EDS1216AATA tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI /CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL ...
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... Precharge b’ High-Z lMRD lRCD Output mask Bank 3 Bank 3 Active Read EDS1216AATA tRP tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI Bank 0 access = VIH or VIL 13 14 ...
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... Bank 0 Active Write Read R:b C:a C a+1 a+3 Bank 0 Bank 0 Bank 3 Write Write Active EDS1216AATA Read cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL b"+1 b"+2 b"+3 Bank 3 Precharge Write cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL ...
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... Active Write R:b C:a a a+1 a+2 a+3 a a+1 a+3 Bank 0 Bank 3 Write Active High Auto Refresh EDS1216AATA Bank 0 Bank 3 Precharge Precharge Bank 0 Precharge Read/Burst write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL C:a R:a a a+1 ...
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... C:b High-Z a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Bank0 Bank3 Write suspend Write suspend Bank3 Precharge Write Active start end Write EDS1216AATA t RC Self refresh cycle Auto Next /RAS-/CAS delay = 3 refresh clock enable VIH or VIL Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 ...
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... Power down entry Power down mode exit Active Bank High Auto Refresh EDS1216AATA Power down cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL code Valid lMRD Bank active Mode register If needed ...
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... Package Drawing 54-pin Plastic TSOP(ll) 1 22.22 ± 0.10 PIN 0.80 0.30 to 0.45 0. 0.71 0. Note: 1. This dimension does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not exceed 0.15mm per side EDS1216AATA Unit: mm 0.80 Nom 0.25 0.50 ± 0.10 ECA-TS2-0102-01 ...
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... Recommended Soldering Conditions Type of Surface Mount Device EDS1216AATA ...
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... ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. EDS1216AATA CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. EDS1216AATA M01E0107 ...