QL3012-3PF100C QuickLogic Corp, QL3012-3PF100C Datasheet
QL3012-3PF100C
Related parts for QL3012-3PF100C
QL3012-3PF100C Summary of contents
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... Up to 308 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades • eight high-drive input/distributed network pins © 2005 QuickLogic Corporation Up to Eight Low-Skew Distributed Networks • Two array clock/control networks are available to the logic cell flip-flop; clock, set, and reset inputs — ...
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... Table 2: Max I/O per Device/Package Combination 84 PLCC 100 TQFP 144 TQFP 110 - 74 110 - - - - QL3012 QL3025 QL3040 15,740 32,616 48,384 320 672 1,008 438 876 1,260 110 196 244 - - - 100 100 - 144 ...
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... FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickTools for designers who use Cadence other third-party tools for design entry, synthesis, or simulation. © 2005 QuickLogic Corporation TM for Workstations package provides a solution TM ...
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... Parameter High Drive Input Delay by the numbers provided in Table 9 Propagation Delays (ns) Fanout 1.4 1.7 1.9 1.7 1.7 1.7 0.0 0.0 0.0 0.7 1.0 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.0 1.3 1.5 0.8 1.1 1.3 1.9 1.9 1.9 1.8 1.8 1.8 ° = 3.3 V and Multiply by the appropriate CC Table 9 . Propagation Delays (ns) Fanout 1.5 1.6 1.8 1.9 2.4 1.6 1.7 1.9 2.0 2.5 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.7 0.8 1.0 1.1 1.6 0.6 0.7 0.9 1.0 1.5 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 ° = 3.3 V and Multiply by the appropriate CC Table 9 . © 2005 QuickLogic Corporation Table 2.2 3.2 1.7 1.7 0.0 0.0 1.5 2.5 1.2 1.2 1.2 1.2 1.8 2.8 1.6 2.6 1.9 1.9 1.8 1 2.9 4.4 3.0 4.5 3.1 3.1 0.0 0.0 2.1 3.6 2.0 3.5 2.3 2.3 0.0 0.0 ...
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... Output Delay Tri-state to Low PZL t Output Delay High to Tri-State PHZ t Output Delay Low to Tri-State PLZ Figure 2 a. The loads presented in are used for t © 2005 QuickLogic Corporation Table 5: Clock Cells Propagation Delays (ns) Loads per Half Column 1 2 1.2 1.2 0.7 0.7 0.8 0.8 Table 6: Input-Only I/O Cells Parameter ...
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... Min. 0 CCIO -0.5 0.3 V 2 GND -10 or GND -10 - GND 0.50 (typ) CCIO 0 “Contact Information” © 2005 QuickLogic Corporation Value ±20 mA ±2000 V 300°C Unit Max. 3 °C - °C 1.85 n/a 1.50 n/a 1.25 n/a 0.88 n/a 0.80 n/a Max. Units +0 0. µA 10 µ ...
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... Kv and Kt Graphs 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 Figure 4: Temperature Factor vs. Operating Temperature -60 © 2005 QuickLogic Corporation Figure 3: Voltage Factor vs. Supply Voltage Voltage Factor vs. Supply Voltage 3 3.1 3.2 3.3 Supply Voltage (V) Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -40 - Junction Temperature C pASIC 3 FPGA Family Data Sheet Rev ...
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... CCIO CC MAX 400 us Time /V rails must take 400 µs or longer to reach the maximum value CC CCIO to the maximum voltage faster than 400 µs can cause the device to behave -V ) CCIO CC MAX V CC ≤ 500 mV when ramping up the power supply. © 2005 QuickLogic Corporation ...
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... TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. © 2005 QuickLogic Corporation Figure 6: JTAG Block Diagram TAp Controller ...
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... Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5.0 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Description if not CC if not CC CC © 2005 QuickLogic Corporation ...
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... GND GCLK ACLK/I 34 © 2005 QuickLogic Corporation Figure 7: QL3004 – 68 Pin PLCC (Top View GND IO GCLK/I ACLK/I VCC GCLK/I GCLK/I pASIC 3 IO QL3004-1PL68C ...
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... VCC 67 GCLK ACLK GND Function 84 PLCC Function I/O 64 ACLK/I I I/O 66 GCLK/I VCCIO 67 VCC I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O TRSTB 73 I/O TMS 74 I/O I/O 75 TCK I/O 76 STM I/O 77 I/O I/O 78 I/O I/O 79 VCC I/O 80 I/O I/O 81 I/O GND 82 GND I I/O © 2005 QuickLogic Corporation ...
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... ACLK/I 13 VCC 14 GCLK/I 15 GCLK/I 16 VCC 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O © 2005 QuickLogic Corporation Figure 9: QL3004 – 100 Pin TQFP (Top View) pASIC 3 QL3004-1PF100C Table 14: QL3004 – 100 TQFP Pinout Table Function 208 PQFP 26 TDI ...
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... GCLK/I 54 GCLK/I 53 VCC 52 51 ACLK/I GCLK GND Function 68 PLCC Function GND 52 VCC I I/O 54 GCLK/I I/O 55 I/O VCCIO 56 I/O I/O 57 I/O I/O 58 I/O TRSTB 58 I/O TMS 60 I/O I/O 61 TCK I/O 62 STM I/O 63 I/O I/O 64 I/O GND 65 I/O I I/O ACLK/I 68 I/O © 2005 QuickLogic Corporation ...
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... GND © 2005 QuickLogic Corporation Figure 11: QL3004E – 84 Pin PLCC (Top View GND IO I ACLK/I I pASIC 3 GCLK/I VCC IO QL3004E-1PL84C IO IO ...
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... TRSTB 74 50 TMS 75 Pin 76 Pin 51 Function 100 TQFP Function I/O 76 TCK I/O 77 STM I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O GND 84 I/O I/O 85 GND I 86 I/O ACLK/I 87 I/O VCC 88 GND I 89 I/O GCLK/I 90 I/O VCC 91 I/O I/O 92 VCCIO I/O 93 I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 TDO © 2005 QuickLogic Corporation ...
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... GND ACLK/I 34 © 2005 QuickLogic Corporation Figure 13: QL3006 – 68-pin PLCC (Top View GND IO I ACLK/I VCC I GCLK/I pASIC 3 IO QL3006-1PL68C Table 18: QL3006 – ...
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... IO 68 VCC 67 GCLK ACLK GND Function 84 PLCC Function I/O 64 ACLK/I I I/O 66 GCLK/I VCCIO 67 VCC I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O TRSTB 73 I/O TMS 74 I/O I/O 75 TCK I/O 76 STM I/O 77 I/O I/O 78 I/O I/O 79 VCC I/O 80 I/O I/O 81 I/O GND 82 GND I I/O © 2005 QuickLogic Corporation ...
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... VCC I/O 50 © 2005 QuickLogic Corporation Figure 15: QL3006 – 100 Pin TQFP (Top View) pASIC 3 QL3006-1PF100C Table 20: QL3006 – 100 TQFP Pinout Table Function 100 TQFP TDI 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 GND 60 I/O 61 ...
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... I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 GND 20 I • • 20 www.quicklogic.com • • • • Figure 16: QL3012 – 84 Pin PLCC (Top View GND IO I ACLK/I I pASIC 3 GCLK/I VCC IO QL3012-1PL84C IO IO ...
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... ACLK/I 13 VCC GCLK/I 16 VCC 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O © 2005 QuickLogic Corporation Figure 17: QL3012 – 100 Pin TQFP (Top View) pASIC 3 QL3012-1PF100C Table 22: QL3012 – 100 TQFP Pinout Table Function 100 TQFP 26 TDI ...
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... FPGA Family Data Sheet Rev. D QL3012 – 144 TQFP Pinout Diagram Pin 1 Pin 37 • • 22 www.quicklogic.com • • • • Figure 18: QL3012 – 144 Pin TQFP (Top View) pASIC 3 QL3012-1PF144C Pin 109 Pin 73 © 2005 QuickLogic Corporation ...
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... GND I/O 74 © 2005 QuickLogic Corporation Table 23: QL3012 – 144 TQFP Pinout Table Function 144 TQFP TDI 75 I/O 76 I/O 77 I/O 78 VCC 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 GND 87 I/O 88 I/O 89 I/O 90 GND 91 I/O 92 I/O 93 ...
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... TRSTB 74 50 TMS 75 Pin 76 Pin 51 Function 100 TQFP Function I/O 76 TCK I/O 77 STM I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O GND 84 I/O I/O 85 GND I 86 I/O ACLK/I 87 I/O VCC 88 GND I 89 I/O GCLK/I 90 I/O VCC 91 I/O I/O 92 VCCIO I/O 93 I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 TDO © 2005 QuickLogic Corporation ...
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... QL3025 – 144 TQFP Pinout Diagram Pin 1 Pin 37 © 2005 QuickLogic Corporation Figure 20: QL3025 – 144 Pin TQFP (Top View) pASIC 3 QL3025-1PF144C pASIC 3 FPGA Family Data Sheet Rev. D Pin 109 Pin 73 www.quicklogic.com • • 25 • • • • ...
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... TCK 133 I/O 110 STM 134 GND 111 I/O 135 I/O 112 I/O 136 I 113 I/O 137 ACLK/I 114 V 138 CC VCC 115 I/O 139 I 116 I/O 140 GCLK/I 117 I/O 141 VCC 118 I/O 142 I/O 119 I/O 143 I/O 120 I/O 144 © 2005 QuickLogic Corporation Function I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO I/O ...
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... QL3025 – 208 PQFP Pinout Diagram Pin 1 Pin 53 © 2005 QuickLogic Corporation Figure 21: QL3025 – 208 Pin PQFP (Top View) pASIC 3 QL3025-1PQ208C pASIC 3 FPGA Family Data Sheet Rev. D Pin 157 Pin 105 www.quicklogic.com • • 27 • • • • ...
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... I/O 195 154 I/O 196 155 I/O 197 156 I/O 198 157 TCK 199 GND 158 STM 200 159 I/O 201 160 I/O 202 161 I/O 203 162 I/O 204 163 GND 205 164 I/O 206 165 VCC 207 166 I/O 208 167 I/O 168 I/O © 2005 QuickLogic Corporation I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O TDO I/O ...
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... QL3025 – 256 PBGA Pinout Diagram Figure 22: QL3025 – 256-Pin PBGA Pinout Diagram 20 © 2005 QuickLogic Corporation TOP View pASIC 3 QL3025-1PB256C BOTTOM View pASIC 3 FPGA Family Data Sheet Rev. D PIN A1 CORNER www.quicklogic.com • ...
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... Y4 I I/O V3 I/O Y6 I/O V4 I/O Y7 I I/O Y9 I/O V7 I/O Y10 NC V8 I/O Y11 I/O V9 I/O Y12 I/O V10 I/O Y13 VCC V11 I/O Y14 VCC V12 VCCIO Y15 I/O V13 I/O Y16 I/O V14 I/O Y17 I/O V15 I/O Y18 NC V16 I/O Y19 I/O V17 I/O Y20 I/O V18 I/O NC V19 TMS © 2005 QuickLogic Corporation Function I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC ...
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... QL3040 – 208 PQFP Pinout Diagram Pin 1 Pin 53 © 2005 QuickLogic Corporation Figure 23: QL3040 – 208 Pin PQFP (Top View) pASIC 3 QL3040-1PQ208C pASIC 3 FPGA Family Data Sheet Rev. D Pin 157 Pin 105 www.quicklogic.com • • 31 • • • • ...
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... I/O 157 TCK 158 STM I/O 159 I/O I/O 160 I/O I/O 161 I/O I/O 162 I/O I/O 163 GND I/O 164 I/O I/O 165 V CC I/O 166 I/O I/O 167 I/O I/O 168 I/O © 2005 QuickLogic Corporation Function 169 I/O 170 I/O 171 I/O 172 I/O 173 I/O 174 I/O 175 I/O 176 I/O 177 GND 178 I/O 179 I/O 180 I/O 181 I/O 182 GND 183 I/O 184 I/O 185 I/O 186 ...
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... QL3040 – 456 PBGA Pinout Diagram Figure 24: QL3040 – 456-Pin PBGA Pinout Diagram © 2005 QuickLogic Corporation pASIC 3 FPGA Family Data Sheet Rev. D TOP View pASIC 3 QL3040-1PB456C BOTTOM View ...
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... R3 M1 ACLK GCLK I/O R11 GND/THERM M4 NC R12 GND/THERM M5 GND R13 GND/THERM M11 GND/THERM R14 GND/THERM M12 GND/THERM R15 GND/THERM M13 GND/THERM R16 GND/THERM © 2005 QuickLogic Corporation Function NC NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND I/O I/O NC I/O I/O I GCLK/I GCLK/I NC ACLK/I NC I/O I/O NC ...
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... I/O AB2 V2 I/O AB3 V3 NC AB4 V4 NC AB5 V5 NC AB6 V22 GND AB7 V23 NC AB8 V24 I/O AB9 V25 NC AB10 V26 I/O AB11 © 2005 QuickLogic Corporation 456 Function I/O AB12 NC AD1 I/O AB13 I/O AD2 I/O AB14 GND AD3 I/O AB15 VCC AD4 NC AB16 I/O AD5 NC AB17 NC AD6 I/O AB18 VCC ...
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... FPGA Family Data Sheet Rev. D QL3060 – 208 PQFP Pinout Diagram Pin 1 Pin 53 • • 36 www.quicklogic.com • • • • Figure 25: QL3060 – 208 Pin PQFP (Top View) pASIC 3 QL3060-1PQ208C Pin 157 Pin 105 © 2005 QuickLogic Corporation ...
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... GCLK VCC VCC 83 42 I/O 84 © 2005 QuickLogic Corporation Table 30: QL3060 – 208 PQFP Pinout Table Function 208 PQFP Function GND 85 I/O I/O 86 I/O I/O 87 I/O I/O 88 I/O I/O 89 I/O I/O 90 I/O I/O 91 I/O I/O 92 I/O I/O 93 I/O I/O 94 I/O I/O 95 GND TDI 96 I/O I/O 97 ...
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... Figure 26: QL3060 – 456-Pin PBGA Pinout Diagram TOP View pASIC 3 QL3060-1PB456C BOTTOM View PIN A1 CORNER © 2005 QuickLogic Corporation ...
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... D15 B17 I/O D16 B18 I/O D17 B19 I/O D18 B20 I/O D19 B21 I/O D20 B22 I/O D21 B23 I/O D22 B24 I/O D23 B25 I/O D24 © 2005 QuickLogic Corporation Table 31: QL3060 – 456 PBGA Pinout Table Function 456 Function STM D25 I/O I/O D26 I/O I/O E1 I/O I/O E2 I/O TDO E3 I/O I/O E4 I/O I/O E5 GND I/O E6 VCC ...
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... TRSTB AF12 AD24 I/O AF13 AD25 I/O AF14 AD26 I/O AF15 AE1 TDI AF16 AE2 I/O AF17 AE3 I/O AF18 AE4 I/O AF19 AE5 I/O AF20 AE6 I/O AF21 AE7 I/O AF22 AE8 I/O AF23 AE9 I/O AF24 AE10 I/O AF25 AE11 I/O AF26 AE12 I/O AE13 I/O AE14 I/O AE15 I/O © 2005 QuickLogic Corporation Function I/O I/O I/O I/O I/O I/O I/O NC TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... Package Mechanical Drawings 68 PLCC Packaging Drawing © 2005 QuickLogic Corporation pASIC 3 FPGA Family Data Sheet Rev. D www.quicklogic.com • • 41 • • • • ...
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... FPGA Family Data Sheet Rev PLCC Packaging Drawing • • 42 www.quicklogic.com • • • • © 2005 QuickLogic Corporation ...
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... TQFP Mechanical Drawing © 2005 QuickLogic Corporation pASIC 3 FPGA Family Data Sheet Rev. D www.quicklogic.com • • 43 • • • • ...
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... FPGA Family Data Sheet Rev. D 144 TQFP Mechanical Drawing • • 44 www.quicklogic.com • • • • © 2005 QuickLogic Corporation ...
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... PQFP Packaging Drawing © 2005 QuickLogic Corporation pASIC 3 FPGA Family Data Sheet Rev. D www.quicklogic.com • • 45 • • • • ...
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... FPGA Family Data Sheet Rev. D 256 PBGA Mechanical Drawing • • 46 www.quicklogic.com • • • • © 2005 QuickLogic Corporation ...
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... PBGA Mechanical Drawing © 2005 QuickLogic Corporation pASIC 3 FPGA Family Data Sheet Rev. D www.quicklogic.com • • 47 • • • • ...
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... Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information). ** Contact QuickLogic regarding availability (see Contact Information) • • 48 www.quicklogic.com • • • • Table 32: Packaging Options Device QL3004E QL3006 QL3012 Pin Pitch Pin Pitch Pin 100 TQFP 100 100 144 0.5 mm 0.5 mm TQFP ...
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... Copyright and Trademark Information Copyright © 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited ...