EM636165TS-6 Etron Technology Inc., EM636165TS-6 Datasheet

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EM636165TS-6

Manufacturer Part Number
EM636165TS-6
Description
Manufacturer
Etron Technology Inc.
Datasheet

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Etron Confidential
Features
• Fast access time: 4.5/5.4/5.4ns
• Fast clock rate: 200/166/143 MHz
• Self refresh mode: standard
• Internal pipelined architecture
• 512K word x 16-bit x 2-bank
• Programmable Mode registers
• Individual byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• JEDEC standard +3.3V ± 0.3V power supply
• Interface: LVTTL
• 50-pin 400 mil plastic TSOP II package
Overview
synchronous DRAM containing 16 Mbits. It is
internally configured as a dual 512K word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 512K x 16 bit banks is organized
as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory bandwidth and particularly well suited to
high performance PC applications
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc. reserves the right to change products or specification without notice.
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
- Optional drive strength control
-Pb and Halogen Free
The EM636165 SDRAM is a high-speed CMOS
The EM636165 provides for programmable Read
FAX: (886)-3-5778671
1M x 16 bit Synchronous DRAM (SDRAM)
Table 2. Ordering Information
TS: indicates TSOP II package
G: indicates Pb and Halogen Free
Figure 1 Pin Assignment (Top View)
Table 1. Key Specifications
t
t
t
t
A10/AP
CK3
RAS
AC3
RC
VDDQ
LDQM
VDDQ
VSSQ
VSSQ
EM636165TS-5
EM636165TS-6
EM636165TS-7
CAS#
RAS#
WE#
Part Number
DQ3
DQ5
VDD
VDD
DQ0
DQ1
DQ2
DQ4
DQ6
DQ7
CS#
A11
A3
A1
A2
A0
Clock Cycle time(min.)
Row Active time (max.)
Access time from CLK (max.) 4.5/5.4/5.4ns
Row Cycle time(min.)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
EM636165
Advanced (Rev.4.0, Nov. /2009)
Frequency
EM636165TS
200MHz
166MHz
143MHz
50
49
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
48
47
VSS
DQ9
DQ8
VDDQ
NC
UDQM
CLK
DQ15
DQ14
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
CKE
A9
VDDQ
NC
A8
A7
A6
A5
A4
VSS
55/60/63 ns
40/42/42ns
-5/6/7
TSOPII
TSOPII
TSOPII
5/6/7
Type
ns

Related parts for EM636165TS-6

EM636165TS-6 Summary of contents

Page 1

... CK3 t Row Active time (max.) RAS t Access time from CLK (max.) 4.5/5.4/5.4ns AC3 t Row Cycle time(min.) RC Table 2. Ordering Information Part Number EM636165TS-5 EM636165TS-6 EM636165TS-7 TS: indicates TSOP II package G: indicates Pb and Halogen Free Figure 1 Pin Assignment (Top View) VDD 1 DQ0 2 3 DQ1 4 VSSQ ...

Page 2

... RAS# COMMAND CAS# DECODER WE# COLUMN A10/AP COUNTER A0 ADDRESS BUFFER A9 A11 REFRESH COUNTER Etron Confidential CONTROL SIGNAL GENERATOR MODE REGISTER 2 EM636165TS 2048x256x16 CELL ARRAY (BANK #0) Column Decoder DQ0 DQs Buffer DQ15 LDQM, UDQM 2048x256x16 CELL ARRAY (BANK #1) Column Decoder Rev. 4.0 Nov. 2009 ...

Page 3

... Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Etron Confidential Table 3. Pin Details of EM636165 Description 3 EM636165TS Rev. 4.0 Nov. 2009 ...

Page 4

... No Connect: These pins should be left unconnected. V Supply DQ Power: Provide isolated power to DQs for improved noise immunity. DDQ ( 3.3V ± 0. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. SSQ ( Supply Power Supply: +3.3V ± 0. Supply Ground SS Etron Confidential EM636165TS 4 Rev. 4.0 Nov. 2009 ...

Page 5

... Idle Idle (SelfRefresh) Active Any ( Active Any (PowerDown) Active Active EM636165TS A11 A A CS# RAS# CAS# WE ...

Page 6

... RCD Bank B R/W A with NOP AutoPrecharge Activate RAS# - Cycle time AutoPrecharge Begin (max.). Therefore, the precharge function must be performed in any RAS RCD 6 EM636165TS (min.) from the time of RCD Tn+4 Tn+5 Tn+6 Bank A Row Addr. ) RRD Bank A NOP NOP Activate Don’t Care (Burst Length = n) (min ...

Page 7

... DOUT A DOUT B DOUT DOUT A DOUT B 0 (Burst Length = 4, CAS# Latency = Bank A NOP NOP NOP Activate (Burst Length ≥ 4, CAS# Latency = 2) 7 EM636165TS NOP NOP NOP NOP DOUT A DOUT DOUT A DOUT A DOUT ...

Page 8

... NOP DOUT A Must be Hi-Z before the Write Command (Burst Length ≧ 4, CAS# Latency = NOP NOP NOP DOUT A DOUT DOUT A 0 (CAS# Latency = EM636165TS NOP WRITE B NOP NOP DIN B DIN B DIN Don’t Care ...

Page 9

... The first data element and the write are registered on the same clock edge WRITE A WRITE B NOP NOP DIN A DIN B DIN B DIN EM636165TS (min.) before the Write command is RCD NOP NOP NOP NOP DIN A don’t care 3 (Burst Length = ...

Page 10

... DIN n N+1 Figure 13. Write to Precharge + t (min full-page burst, only the write operation is performed WRITE A NOP NOP NOP Auto Precharge DIN A DIN EM636165TS NOP NOP NOP NOP DOUT B DOUT B DOUT DOUT B DOUT B DOUT B DOUT ...

Page 11

... Vendor Use Only 0 1 Vendor Use Only MRD Address Key t RP Mode Register Set Command Figure 15. Mode Register Set Cycle 11 EM636165TS Burst Length A3 Burst Type 0 Sequential 1 Interleave A1 A0 Burst Length ...

Page 12

... EM636165TS Interleave ...

Page 13

... Reserved 0 2 clocks 1 3 clocks X Reserved Test Mode normal mode Vendor Use Only Vendor Use Only Write Burst Mode Burst-Read-Burst-Write Burst-Read-Single-Write Drive Strength Full Weak 13 EM636165TS Address Field Extended Mode Register Rev. 4.0 Nov. 2009 ...

Page 14

... DOUT A DOUT Burst WRITE A NOP NOP Stop DIN A DIN A DIN A don’t care EM636165TS NOP NOP NOP NOP DOUT A 3 DOUT A DOUT (Burst Length > 4, CAS# Latency = NOP NOP NOP ...

Page 15

... LDQM/UDQM is also used for device selection, byte selection and bus control in a memory system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15. Etron Confidential (min.). To provide the AutoRefresh command, both banks need RC (min), must be met before successive auto refresh operations are RP (min.) because time is required for the XSR 15 EM636165TS Rev. 4.0 Nov. 2009 ...

Page 16

... Input Capacitance I C Input/Output Capacitance I/O Note: These parameters are periodically sampled and are not 100% tested. Etron Confidential Item Parameter ≤ OUT DDQ = 3.3V 1MHz ° Parameter 16 EM636165TS Rating Unit -5/6/7 - 1.0 ~ 4.6 V -1 ° 125 ° C 260 ° 0~70 ° ...

Page 17

... Self Refresh Current CKE ≤ 0.2V ; for other inputs V Etron Confidential = 3.3V ± 0.3V 0~70 ° Symbol DD2PS (min ∞ DD3NS CK ≤ 0.2V ≧ 0.2V EM636165TS - Max. 100 DD1 DD2N DD2P DD3N ...

Page 18

... VIH (Max) = 4.6V for pulse width ≤ 3ns.VIL (Min) = -1.5V for pulse SS . Input signals are changed one time during every EM636165TS -6 -7 Unit Note Min. Max. Min. Max 100K 42 100K ...

Page 19

... Transition (rise and fall) of input signals are in a fixed -0.5) ns should be added to the parameter & and V (simultaneously) when CKE= “L”, DQM= “H” and all input DD DDQ levels) to ensure DQ output is in high impedance EM636165TS 1.4V / 1.4V 2.4V / 0.4V 1ns 1.4V 1.4V 50Ω Z0=50Ω 30pF Rev. 4.0 Nov. 2009 ...

Page 20

... RBx RBx CBx t DAL t RC Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Write with Activate Auto Precharge Command Command Bank B Bank B 20 EM636165TS Begin Auto Precharge Bank B RAy RAy CAy Bx3 Ay0 Ay1 Ay2 Ay3 Activate Write Command Command Bank A Bank A Rev ...

Page 21

... RAS Ax0 Ax1 t OH Read with Read Activate Auto Precharge Command Command Bank A Bank B Command Bank B 21 EM636165TS t IH RAy RAy t RP Bx0 Bx1 t HZ Precharge Activate Command Command Bank A Bank A Don’t Care Rev. 4.0 Nov. 2009 ...

Page 22

... DQM DQ Precharge All Auto Refresh Command Command Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t RC Auto Refresh Command 22 EM636165TS RAx RAx CAx RCD Activate Read Command Command Bank A Bank A Rev. 4.0 Nov. 2009 ...

Page 23

... Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Minimum for 2 Refresh Cycles are required t MRD (*) 1st Auto Refresh Command 23 EM636165TS Any (*) 2nd Auto Refresh Command Command Don’t Care Rev. 4.0 Nov. 2009 ...

Page 24

... Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 *Note 5 *Note 3,4 t *Note 6 *Note 7 Hi-Z Self Refresh Exit is required before exit from SelfRefresh. RAS 24 EM636165TS *Note 8 t XSR t PDE *Note 9 Auto Refresh Don’t Care Rev. 4.0 Nov. 2009 ...

Page 25

... Command Bank A Bank A Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax0 Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles 25 EM636165TS t HZ Ax3 Clock Suspend 3 Cycles Don’t Care Rev. 4.0 Nov. 2009 ...

Page 26

... Command Bank A Bank A Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax0 Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles 26 EM636165TS t HZ Ax3 Clock Suspend 3 Cycles Don’t Care Rev. 4.0 Nov. 2009 ...

Page 27

... Command Write Bank A Command Bank A Etron Confidential T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx1 DAx2 Clock Suspend Clock Suspend Clock Suspend 3 Cycles 1 Cycle 2 Cycles 27 EM636165TS DAx3 Rev. 4.0 Nov. 2009 Don’t Care ...

Page 28

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t IS CAx Ax0 Ax1 Ax2 Read Clock Suspension Clock Suspension Command Start End Bank A 28 EM636165TS (Burst Length=4, CAS# Latency=2) Valid t HZ Ax3 PRECHARGE Precharge STANDBY Command Bank A Power Down Mode Entry Rev. 4.0 Nov. 2009 t ...

Page 29

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Read Read Command Command Bank A Bank A 29 EM636165TS RAz RAz CAz Ay1 Ay2 Ay3 Precharge Activate Read Command Command Command Bank A Bank A Bank A Rev. 4.0 Nov. 2009 Az0 Don’ ...

Page 30

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Read Read Command Command Bank A Bank A 30 EM636165TS RAz RAz CAz Ay0 Ay1 Ay2 Ay3 Precharge Activate Read Command Command Command Bank A Bank A Bank A Rev ...

Page 31

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBx CBy DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 Write Write Command Command Bank B Bank B 31 EM636165TS RBz RBz DBy3 Precharge Activate Command Command Bank B Bank B Rev. 4.0 Nov. 2009 CBz DBz0 DBz1 ...

Page 32

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Activate Read Command Command Bank A Bank A 32 EM636165TS RBy RBy t RP Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Activate Command Bank B Precharge Command Bank B Rev. 4.0 Nov. 2009 CBy ...

Page 33

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx t AC Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Activate Read Command Command Bank A Bank A 33 EM636165TS RBy RBy CBy t RP Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Precharge Activate Read Command Command Command Bank B ...

Page 34

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBx RBx CBx t WR* DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 Activate Write Command Command Bank B Bank B 34 EM636165TS RAy RAy CAy WR* DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 Precharge Activate Write Command ...

Page 35

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Write Command Bank A 35 EM636165TS CAz DAy3 Az0 Az1 The Write Data Read is Masked with a Command Zero Clock Bank A Latency Rev ...

Page 36

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax0 Ax1 Ax2 Ax3 DAy0 Write Command Bank A 36 EM636165TS CAz DAy1 DAy3 Az0 Az1 The Write Data is Masked with a Zero Clock Read Latency Command Bank A Rev ...

Page 37

... RBx CBw CBx t AC Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Activate Read Read Command Command Command Bank B Bank B Bank B 37 EM636165TS CBy CAy CBz Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Read Read Read Precharge Command Command Command Command Bank A Bank B ...

Page 38

... AC Ax0 Ax1 Ax2 Ax3 Bx0 Read Read Read Command Command Command Bank B Bank B Bank B Activate Command Bank B 38 EM636165TS CAy Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Precharge Precharge Read Command Command Command Bank B Bank A Bank A Rev. 4.0 Nov. 2009 Ay3 Don’ ...

Page 39

... CBw CBx CBy DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 Write Write Write Command Command Command Bank B Bank B Bank B Activate Command Bank B 39 EM636165TS CAy CBz DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Write Write Command Command Bank B Bank A ...

Page 40

... Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Read with Activate Read with Auto precharge Auto Precharge Command Command Bank B Command Bank A Bank B 40 EM636165TS Begin Auto Precharge Bank A RBy RBy CBy t RP Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Activate Read with Command ...

Page 41

... RP Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Read with Read with Auto Precharge Auto Precharge Command Command Bank B Bank A 41 EM636165TS Begin Auto Precharge Bank A RBy RBy CBy Bx3 Ay0 Ay1 Ay2 Ay3 By0 Read with Activate Auto Precharge Command Command ...

Page 42

... CBx CAy t DAL DBx2 DBx3 DAy0 DAy1 Write with Write with Auto Precharge Auto Precharge Command Command Bank B Bank A 42 EM636165TS Begin Auto Precharge Bank A RBy RBy CBy DAy2 DAy3 DBy0 DBy1 DBy2 Write with Activate Auto Precharge Command Command Bank B Bank B Rev ...

Page 43

... Command page address back to zero Bank B during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 43 EM636165TS Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Precharge Command ...

Page 44

... The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 44 EM636165TS RBy RBy Bx+1 Bx+2 Bx+3 ...

Page 45

... Full Page burst operation does not page address back to zero terminate when the burst length is satisfied; during this time interval the burst counter increments and continues bursting beginning with the starting address 45 EM636165TS RBy RBy Data is ignored DBx+3 DBx+4 DBx+5 Precharge ...

Page 46

... Day2 Ax1 Ax2 Ax3 DAy0 DAy1 Upper Byte Upper Byte Lower Byte Write is masked is masked is masked Command Bank A 46 EM636165TS CAz Az1 Az2 DAy3 Az0 Az1 Az2 Az3 Read Command Lower Byte Lower Byte Bank A is masked is masked Don’t Care ...

Page 47

... RBv Bu0 Bu1 Bu2 Bu3 Au0 Au1 Au2 Au3 Read Activate Bank A Command with Auto Bank B Precharge 47 EM636165TS Begin Auto Precharge Bank B RAv RBw CBv RAv CAv t RP Bv0 Bv1 Bv2 Bv3 Av0 Read Activate Activate Bank A Command Command ...

Page 48

... Ax0 Ax1 Bx0 Ay0 Ay1 By0 By1 Read Read Read Command Command Command Bank B Bank B Bank A Read Command Bank A 48 EM636165TS RBw CBz RBw t RP Az0 Az1 Az2 Bz0 Bz1 Bz2 Precharge Read Activate Command Command Bank B Command Bank B (Precharge Temination) Bank B Rev ...

Page 49

... CAz DAy1 DBy0 DBy1 DAz0 DAz1 Write Write Write Command Command Command Bank B Bank B Bank A Write Command Bank A 49 EM636165TS CBz DAz2 DBz0 DBz1 DBz2 Write Precharge Command Command Bank B Bank B (Precharge Temination) Write Data are masked Rev. 4.0 Nov. 2009 ...

Page 50

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAy RAy CAy t RP Precharge Activate Read Command Command Command Bank A Bank A Bank A 50 EM636165TS RAz RAz t RP Ay0 Ay1 Ay2 Precharge Termination Precharge Activate of a Read Burst Command Command Bank A Bank A Don’ ...

Page 51

... EM636165TS θ° Dimension in mm Normal Max 1.20 - 0.125 0.20 1.0 1.1 0.45 - 0.155 - 20.95 21.08 10.16 10.29 0.80 - 11.76 11.96 0.50 0.60 0.80 - ...

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