82C931 ETC-unknow, 82C931 Datasheet
82C931
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82C931 Summary of contents
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... OPTi ® Integrated Audio Controller 82C931 Plug and Play Data Book 912-3000-035 Revision: 2.1 August 1, 1997 ...
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Copyright Copyright © 1996, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, tran- scribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, ...
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... Plug and Play ....................................................................................................................................19 4.2 16-Bit Codec/Mixer ...........................................................................................................................20 4.2.1 Codec ...................................................................................................................................20 4.2.2 Mixer.....................................................................................................................................21 4.3 Frequency Synthesizer ....................................................................................................................22 4.4 16-Bit Type F DMA Playback ...........................................................................................................23 4.5 Modem Interface ...............................................................................................................................23 4.6 Push Button Volume Control...........................................................................................................23 4.7 External Serial EEPROM ..................................................................................................................23 4.8 Serial Audio Interface .......................................................................................................................23 4.8.1 I2S-justified format and its variations....................................................................................23 4.8.2 Sony format ..........................................................................................................................24 912-3000-035 Revision: 2.1 Table of Contents 82C931 OPTi ® Page iii ...
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... Table of Contents (cont.) 4.8.3 AT&T PCM codec T7525 compatible 16-bit mono format ....................................................24 4.8.4 Testing I2S format (ZV port) with Audio Precision machine .................................................24 4.8.5 Relevant MC register settings ..............................................................................................24 4.8.6 ZV-Port I2S...........................................................................................................................25 4.8.6.1 LRCLK ..................................................................................................................25 4.8.6.2 SDATA ..................................................................................................................25 4.8.6.3 SCLK.....................................................................................................................26 4.8.6.4 MCLK ....................................................................................................................26 4.8.7 Advanced Precision General Purpose Serial Port................................................................26 4.8.8 TDA1311 Stereo Continuous Calibration .............................................................................27 5.0 Register Descriptions .................................................................................................... 29 5 ...
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... RESET and CLK Timing Waveform...............................................................................................50 Figure 6-2 CD-ROM I/O Read Cycle...............................................................................................................51 Figure 6-3 CD-ROM I/O Write Cycle...............................................................................................................51 Figure 6-4 DMA Write/Playback Cycle............................................................................................................52 Figure 6-5 DMA Read/Capture Cycle .............................................................................................................52 Figure 7-1 100-pin PQFP, Plastic Quad Flat Pack .........................................................................................53 Figure 7-2 100-pin TQFP, Thin Quad Flat Package .......................................................................................54 912-3000-035 Revision: 2.1 List of Figures 82C931 OPTi ® Page v ...
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... OPTi ® Page vi 912-3000-035 Revision: 2.1 ...
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... Mode Alphabetical Pin Cross-Reference List..................................................................... 7 Table 3-6 931-AD Mode Numerical Pin Cross-Reference List ......................................................................13 Table 3-7 931-AD Mode Alphabetical Pin Cross-Reference List ...................................................................13 Table 4-1 FS Output Frequencies .................................................................................................................22 Table 5-1 82C931 I/O Base Addresses .........................................................................................................29 Table 5-2 82C931 Register Map....................................................................................................................29 Table 5-3 MCBase, Direct MC Register.........................................................................................................30 Table 5-4 McBase, Index (MCIndx) and Data (MCData) Ports Address Range............................................30 Table 5-5 MCIdx and MCData Registers ...
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... OPTi ® Page viii OPTi Confidential 912-3000-035 Revision: 2.1 ...
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... Sound Blaster Pro, Windows Sound System, FM synthesis - MPU-401 MIDI interface - CD-ROM interface - Joystick/game port - Modem interface - 82C931 control • Supports external serial EEPROM (optional) • External modem chipset interface Figure 1-1 System Block Diagram 912-3000-035 Revision: 2.1 • Full duplex operation: record and playback simultaneously using two 8- or 16-bit DMA channels • ...
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... OPTi ® Page 2 912-3000-035 Revision: 2.1 ...
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... The 82C931 Integrated Audio Controller provides all of the functions and interfaces for Sound Blaster Pro-compatible and Microsoft Windows Sound System-compatible cards. The 82C931 is intended to provide an integrated audio solu- tion for business audio, educational/entertainment sound, and multimedia applications. ISA ...
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... Figure 2-2 Data Flow Block Diagram Note: There are four signals which are referenced by acronyms to make connections within the block diagram. HCO = Host Capture Output HPO = Host Playback Output FMO = FM Output SI = Serial Serial Out OPTi ® Page 4 912-3000-035 Revision: 2.1 ...
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... Mode - Single chip adaptor card with support for IDE CD-ROM and modem interfaces. Pins 11 is used to select the desired mode of the 82C931 (as shown in Table 3-1). Table 3-2 details the features in both of these modes. Table 3-1 Mode Selection ...
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... SD11 19 SD10 20 SD9 21 SD8 22 GD0 23 GD1 24 GD2+FSYNC 25 GD3+SCLK 26 GND 27 GD4+VOLDN 28 GD5+VOLUP 29 GD6+SADO+VOLDWN 30 * Pinout for TQFP Package is identical to pinout for PQFP Package. OPTi ® Page 6 * 82C931 931-MB Mode 80 SA8 79 SA7 78 SA6 77 SA5 76 SA4 75 SA3 74 SA2 73 SA1 72 SA0 71 SD7 70 SD6 69 SD5 68 SD4 67 VCC ...
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... I/O SA2 36 I/O SA3 49 I SA4 50 I SA5 54 I/O SA6 55 I/O SA7 56 I/O SA8 53 I/O SA9 52 I/O SA10 96 I SA11 99 I SA12 97 I 82C931 Pin Pin Type No. Pin Name Type I 76 SA4 I/O 77 SA5 I/O 78 SA6 I/O 79 SA7 I/O 80 SA8 I/O 81 SA9 G 82 SA10 P 83 SA11 O-TS 84 RESET O-TS 85 AGND O-TS 86 VREF2 I/O 87 AVCC I/O 88 CINR I/O 89 MIXOUTR I/O 90 CINL ...
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... Mode Signal Descriptions 3.2.1.1 ISA Bus Interface Signals Signal Name Pin No. IOW# 49 IOR# 50 AEN 51 RESET 84 SA[15:0] 38, 39, 41, 42, 83:72 SD[15:8] 13:16, 19:22 SD[7:0] 71:68, 65:62 DACK0# 46 DACK1# 47 DACK3# 48 DRQ0 59 DRQ1 60 DRQ3 61 DACK5# 44 DACK6# 45 DRQ5 32 DRQ6 33 IRQ5 54 IRQ7 55 IRQ9 56 IRQ10 53 IRQ11 52 3.2.1.2 MIDI Interface Signals Signal Name Pin No. RXD 9 TXD ...
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... General Purpose Input/Output I/O-TTL, PU (8mA) 931 Mode Configuration Bit 0: This pin is used to configure the 82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1). These settings are latched into the 82C931 at reset. General Purpose Input/Output I/O-TTL, PD (12mA) External Serial EEPROM Clock ...
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... Mode Signal Descriptions (cont.) 3.2.1.4 Game Port and Serial Audio Interface Signals Signal Name Pin No. GD4 28 VOLDN GD3 26 SCLK GD2 25 FSYNC GD1 24 GD0 23 3.2.1.5 Codec/Mixer Interface Signals Signal Name Pin No. MICL 97 MICR 98 LINEL 96 LINER 99 CDL 95 CDR 100 AUXL 94 AUXR 1 OUTL 92 OUTR ...
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... Signal Description I-Analog Oscillator Input: A 14.318MHz crystal oscillator connected across this pin and the OSCO pin. O-Analog Oscillator Output: See OSCI. Signal/Pin Type (Drive) Signal Description Power Connection P Ground Connection G P Analog Power Connection G Analog Ground Connection 82C931 OPTi ® Page 11 ...
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... GD1 GD2+IRQ3 GD3+IRQ4 GND GD4+VOLDN GD5+VOLUP GD6+MODEMINT+VOLDWN * Pinout for TQFP Package is identical to pinout for PQFP Package. OPTi ® Page 82C931 14 15 931-AD Mode SA8 79 SA7 78 SA6 ...
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... RESET ROMCS+PNPEN 43 I/O RXD 11 I/O SA0 38 O SA1 39 O SA2 41 I/O SA3 54 I/O SA4 55 I/O SA5 56 I/O SA6 53 I/O SA7 52 I/O SA8 42 I/O SA9 82C931 Pin Pin Type No. Pin Name I 76 SA4 I 77 SA5 I/O 78 SA6 I/O 79 SA7 I/O 80 SA8 I/O 81 SA9 I/O 82 SA10 G 83 SA11 P 84 RESET O-TS 85 AGND O-TS 86 VREF2 O-TS 87 AVCC I/O 88 CINR I/O 89 MIXOUTR I/O 90 CINL I/O ...
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... Mode Signal Descriptions 3.3.1.1 ISA Bus Signals Signal Name Pin No. IOW# 49 IOR# 50 AEN 51 RESET 84 SA[15:0] 13:16, 83:72 SD[7:0] 71:68, 65:62 DACK0# 46, DACK1# 47, DACK3# 48 DRQ0 59 DRQ1 60 DRQ3 61 GPIO0 43 EXTROM# IRQ5 54 IRQ7 55 IRQ9 56 IRQ10 53 IRQ11 52 IRQ15 42 GPIO3 3.3.1.2 MIDI Interface Signals Signal Name Pin No. RXD 9 TXD 10 OPTi ® Page 14 ...
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... General Purpose I/O Bit 1 I/O-TTL, PU (8mA) 931 Mode Configuration Bit 0: This pin is used to configure the 82C931 in either the 931-MB or 931-AD mode (refer to Table 3-1). These settings are latched into the 82C931 at reset. IDE CA2: Buffered SA2 for CD-ROM I/O-TTL, PD (12mA) External Serial EEPROM Clock IDE Disable: Jumper selection to disable IDE resource ...
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... Mode Signal Descriptions (cont.) 3.3.1.4 Game Port and Modem Interface Signals Signal Name Pin No. GD7 31 MODEMCS# MODEM# VOLUP GD6 30 MODEMINT VOLDWN GD5 29 VOLUP GD4 28 VOLDN GD3 26 IRQ4 GD2 25 IRQ3 GD1 24 GD0 23 3.3.1.5 Codec/Mixer Interface Signals Signal Name Pin No. MICL 97 MICR 98 LINEL ...
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... Type (Drive) Signal Description I-TTL Serial Audio Data Input O-TTL Serial Audio Data Output Serial Audio Clock I/O-TTL I/O-TTL Serial Audio Synchronization Signal/Pin Type (Drive) Signal Description P Power Connection Ground Connection G Analog Power Connection P G Analog Ground Connection 82C931 OPTi ® Page 17 ...
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... OPTi ® Page 18 912-3000-035 Revision: 2.1 ...
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... Functional Description The 82C931 is an optimized single chip solution with built-in Plug-and-Play functions, built-in FM synthesizer and 16-bit Sigma-Delta Codec to provide all of the features needed to create the following sound characteristics and applications: • 16-bit sound quality Sound Blaster Pro and Windows Sound System compatible card • ...
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... Codec/Mixer 4.2.1 Codec Features of the built-in 16-bit stereo sigma-delta codec include: • Sigma-delta stereo ADC with 128X over-sampling • Sigma-delta stereo DAC with 128X over-sampling • On-chip 8X Interpolation Filter • On-chip analog post filter • Single-ended input and output • Sampling rate of 5KHz to 48KHz ...
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... Table 5-11 in the Register Section. Figure 4-2 shows a functional block diagram of the mixer Mux Zero Cross Detect 2 2 Mixer Latch Control 82C931 2 2 Gain MIXOUTL/R (16 Levels 22.5dB (1.5dB step) 2 Master Volume ATTEN/MUTE OUTL/R (32 Levels -93dB (3dB steps) OPTi Page 21 ® ...
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... Frequency Synthesizer The Frequency Synthesizer (FS) block generates the codec sampling clock from a reference crystal oscillator of 14.318MHz. The output frequency of the FA is equal to 256 times fs (where fs = codec sampling frequency). One of the 236 frequencies may be generated by the FS. The selection of the FS output frequency is done via programming eight register bits in the Digital Audio Processor Write Com- mand/Data (40h/FSEL[7:0]) ...
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... The 82C931 provides a serial EEPROM interface that is com- patible with devices from a number of vendors. A 512- byte EEPROM is sufficient for information required by PnP. Pin 35 of the 82C931 provides the data clock for the EEPROM. Pin 36 provides data to the EEPROM, while pin 37 gets input from the EEPROM. ...
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... To program the 931 in the I S-justified mode, the MC22 and MC21 registers need to be set. The relevant MC22 and MC21 bit definitions are shown below for reference S-justified mode (ZV-port): MC22[7:0] = "00110001" (31H). MC21[7:0] = "10000010" (82H). 2 There are other I S variations: left-justified and right-justified ...
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... Digital audio data is transferred using the I mat Format 2 The I S format is shown below. The digital audio data is left channel-MSB justified to the high-to-low going edge of the LRCLK plus one SCLK delay. Right Channel 82C931 Default: 00h bit 2 bit 1 ADCSEL FDACSEL SDATA OPTi bit 0 DACSEL 2 S for- ® ...
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... SCLK This signal is the serial digital audio PCM clock. 4.8.6.4 MCLK This signal is the Master clock for the digital audio. MCLK is asynchronous to LRCLK, SDATA and SCLK. The MCLK must be either 256x or 384x the desired Input Word Rate (IWR). IWR is the frequency at which words for each channel are input to the DAC and is equal to the LRCLK frequency ...
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... TDA1311 Stereo Continuous Calibration Figure 4-5 Format of Input Signals DATA MSB BCK WS SAMPLE OUT 912-3000-035 Revision: 2.1 LSB LEFT 82C931 MSB LSB RIGHT MKA488 OPTi Page 27 ® ...
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... OPTi ® Page 28 912-3000-035 Revision: 2.1 ...
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... Under this design scheme, the only fixed I/O port used by 82C931 is at 0F8Dh. The MC address and data I/O port addresses are fully pro- grammable, from 0E0Eh-0EFEh (address port) and 0E0Fh- 0FFFh (data port) ...
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... To access MCIR1-23, write the corresponding register index into the address access port and read (or write) the data from (or to) the data access port. This read or write is only possible if the correct password (E4h) has been written into Port 0F8Dh disabled (0F8Dh[7] = 1). ...
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... Default = 00h Volume effect DMA watch Reserved for Sound dog timer: Blaster Pro 0 = Disable mixer voice vol Enable ume emulation: When enabled Disable the 82C931 will 1 = Enable generate inter- nal DACK after the DRQ pend- ing time-up. OPTi 0 (1) (1) (1) (1) ® ...
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... Disable uration man Disable 1 = Enable ager assigned 1 = Enable a CSN to (1) 82C931. (1) When a CSN is assigned to the 82C931, it switches to the PNP mode and the resource configuration is controlled through the PNP regis- ters. OPTi ® Page MIDI Interface Register (WO) MPU-401 interrupt select: ...
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... Table 5-6 MC Indirect Registers (cont MCIR14 PNP card select number: This registers shows the CSN assigned to the 82C931 by the PNP configuration manager. MCIR15 PNP READ_DATA port: This registers shows the READ_DATA port assigned by the PNP configuration manager. MCIR16 Reserved Push-bottom UP bottom is ...
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... Table 5-6 MC Indirect Registers (cont MCIR19 IDE IRQ input SDHOE IRQ3, IRQ4: routed to IRQ function on pin 0 = Disable output: 43 when config Enable ured for Disable Mode Enable 0 = Disable 1 = Enable MCIR20 GPIO3 GPIO3 GPIO2 mapping: pin type: mapping Pin Input ...
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... Multiply FDAC auto-switching data by 2 timer test mode Disabled to TxD timer tog Enabled gled by 14.318MHz (default = 31KHz Disabled 1 = Enabled 82C931 2 1 Default = 00h CLKSEL[1:0] Selects shift clock for serial audio data output (sclk_out mclk mclk mclk mclk/1 Default = 00h ACTBX ACTAY ...
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... SBBase Register SBBase is mainly used to access the Digital Audio Processor (DAP) registers, however, as shown in Table 5-7 other types of registers are also accessible through SBBase. The index- ing scheme is the same as when accessing MCBase regis- Table 5-7 SBBase Registers for FM and DAP Applications ...
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... WSS Configuration Register (W0) WSS IRQ select: 000 = Disable 001 = IRQ7 010 = IRQ9 011 = IRQ10 100 = IRQ11 101 = IRQ5 110 = Reserved 111 = Reserved WSS Version Register (R0) Version: 04h 82C931 Default = 00h WSS DRQ select: Playback Capture 000 = Disable Disable ...
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... Indirect Register which is indexed by the value most recently written to the Codec Index Address Register. Table 5-9 WSBase Register for Codec/Mixer Applications 7 6 WSBase+04h Codec Index Address Register (R/W, exists in Codec and shadowed in 82C931) Initialization: Mode change: Transfer request: This bit is set 0 = Disable when the ...
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... Upper (or therefore either any 8-bit mode) an overrun for read) ADC capture or underrun for DAC playback (2) has occurred. read) 82C931 2 1 Default = 44h PIO playback PIO Playback Interrupt: data is needed Data Register 0 = Disable for right or left ready for more 1 = Enable ...
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... Table 5-10 Codec Indirect Registers D7 D6 CIR0 Source select: MIC +20dB 00 = LINE 10 = MIC MIXER 0 = Disable 1 = Enable CIR1 Source select: MIC +20dB 00 = LINE 10 = MIC MIXER 0 = Disable 1 = Enable CIR2 Mute: Reserved 0 = Disable 1 = Enable CIR3 Mute: Reserved 0 = Disable 1 = Enable CIR4 Mute: Reserved ...
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... Reserved 1100 = 48.0kHz 1110 = 9.6kHz Interface Configuration Register Reserved Autocalibrate Disable 1 = Enable (autocalibration after power down/reset or mode change 82C931 D2 D1 Default = 80h 10000 = –24.0 11000 = –36.0 10001 = –25.5 11001 = –37.5 10010 = –27.0 11010 = –39.0 10011 = –28.5 11011 = –40.5 10100 = –30.0 11100 = – ...
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... Table 5-10 Codec Indirect Registers (cont CIR10 2. In Sound Blaster mode, the software driver should set bit CIR11 Capture Playback Autocalibration (1) (1) state: overrun: underrun progress This bit is set This bit is set when capture when playback 1 = Not in data has not ...
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... LINER Input Control Register Gain select for LINER inputs (dB): Refer to CIR2[4:1] for decode. MICL Input Control Register Gain select for MICL (dB): Refer to CIR2[4:1] for decode. MICR Input Control Register Gain select for MICR (dB): Refer to CIR2[4:1] for decode. 82C931 Default = 00h Default = 88h ...
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... Table 5-11 Expanded Mode CIR (cont CIR22 Mute: Reserved 0 = Disable 00000 = Enable 00001 = –3 00010 = –6 00011 = –9 00100 = –12 00101 = –15 00110 = –18 00111 = –21 CIR23 Mute: Reserved 0 = Disable 1 = Enable CIR24-CIR27 CIR28 Audio data format - linear PCM or companded ...
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... ESD senstive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the 82C931 features ESD protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pre- cautions are recommended to avoid performance degradation or loss of functionality ...
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... General Specifications: 5.0 Volt Symbol Parameter IIL Low Level Input Current IIH High Level Input Current IOZ Tristate Output Leakage Current V- Schmitt Negative Threshold V+ Schmitt Positive Threshold VH Schmitt Hysteresis VIL low Level Input Voltage VIH High Level Input Voltage VOL Low Level Output Voltage ...
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... Typ Max Unit dB – 22.5 –93 0 –46 2.6 3.0 3.4 1.3 1.5 1.7 2.6 3.0 3.4 2.0 3.0 4.0 1.3 1.5 1.7 –80 dB – –0.5 0.5 dB 100 ppm/ C 82C931 Condition Sine Wave Sine Wave Load = 10K , 25pF Sine Wave DC DC Test Conditions Input @ 1Hz, 2.5Vpp wrt ACOM 90 to -81dB) (-84 to -93dB) OPTi ® Page 47 ...
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... DAC test conditions 16-bit linear mode, Full Scale input ADC test conditions 16-bit linear mode Gain, Line Input. 6.6.1 Analog Inputs Parameters Input voltage LINE/CD/AUX/CIN MIC with 0dB gain MIC with 20dB gain Input impedance Input capacitance 6.6.2 Analog Outputs (10k , 25pF) Parameters Full-scale output voltage (OUTR & ...
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... Min Typ -0.5 100 Min Max Unit 14.0 14.5 MHz MHz 120 82C931 Max Units bits dB .025 % dB +0.5 dB ppm/ C Max Units bits dB .022 % dB +0.5 dB ppm/ C Condition OPTi ® Page 49 ...
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... Symbol Parameter tASU Address Setup to IOR#/IOW# Falling tAHD Address Hold from IOR#/IOW# Rising tDKSU DACK# Setup to IOR#/IOW# Falling tDKHD DACK# Hold from IOR#/IOW# Rising tDHR SD Hold from IOR# Rising tDRHD DRQ Hold from IOR#/IOW# Falling ...
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... Note: For the above timing, AEN = 0, DRQ = 0, and DACKn Figure 6-3 CD-ROM I/O Write Cycle SA[15:0] SD[7:0] tWDSU IOW# tASU tCA CA[2:0] tXCS IDECSn# XIOW# Note: For the above timing, AEN = 0, DRQ = 0, and DACKn 912-3000-035 Revision: 2.1 tCMDW tCMDD tCMDW tCMDD 82C931 tAHD tRDHD tAHD tWDHD OPTi ® Page 51 ...
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... Figure 6-4 DMA Write/Playback Cycle DRQ DACKn# SD[7:0] tDKSU IOW# tCMDD XIOW# Note: For the above timing, AEN = 1. Figure 6-5 DMA Read/Capture Cycle DRQ DACKn# SD[7:0] tDKSU IOR# tCMDD XIOR# Note: For the above timing, AEN = 1. OPTi ® Page 52 tDKHD tCMDW tDKHD tCMDW tWDHD ...
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... Mechanical Packages Figure 7-1 100-pin PQFP, Plastic Quad Flat Pack 912-3000-035 Revision: 2.1 82C931 OPTi ® Page 53 ...
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... Figure 7-2 100-pin TQFP, Thin Quad Flat Package Note: Pinout for TQFP package is identical to pinout of PQFP package. OPTi ® Page 54 912-3000-035 Revision: 2.1 ...
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OPTi ® Michigan HEADQUARTERS: Jay Marketing OPTi Inc. 44752 Helm Street., Ste. A 888 Tasman Drive Plymouth, MI 48170 Milpitas, CA 95035 tel: 313-459-1200 tel: 408-486-8000 fax: 313-459-1697 fax: 408-486-8011 New Jersey SALES OFFICES: S-J Associates, Inc. 131-D Gaither Dr. ...
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OPTi Inc. 888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 www.opti.com ...