SI3024-KS ETC-unknow, SI3024-KS Datasheet
SI3024-KS
Available stocks
Related parts for SI3024-KS
SI3024-KS Summary of contents
Page 1
Features Complete DAA includes the following: 3 Digital/Analog Power Supplies JATE Filter Option 86 dB Dynamic Range TX/RX Paths Daisy-Chaining for Up ...
Page 2
Rev. 1.2 ...
Page 3
Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Electrical Specifications Table 1. Recommended Operating Conditions 1 Parameter Ambient Temperature Si3021 Supply Voltage, Analog 3 Si3021 Supply Voltage, Digital Notes: 1. The Si3035 specifications are guaranteed when the typical application circuit (including component tolerances) and ...
Page 5
Table 3. DC Characteristics ±5 ±5 70°C for K-Grade Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level ...
Page 6
Table 5. AC Characteristics (V = Charge Pump +3.3 V ± 0 Parameter 1 Sample Rate PLL1 Output Clock Frequency Transmit Frequency Response Receive Frequency Response 2 Transmit Full Scale ...
Page 7
Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3021 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation ...
Page 8
Table 8. Switching Characteristics—Serial Interface (DCE = Charge Pump 3 Parameter Cycle time, SCLK SCLK duty cycle Delay time, SCLK to FSYNC Delay time, SCLK ...
Page 9
Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay Time, SCLK ...
Page 10
Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to ...
Page 11
Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V = Charge Pump ±5%, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay ...
Page 12
Input Frequency—Hz Figure 6. FIR Receive Filter Response Input Frequency—Hz Figure 7. FIR Receive Filter Passband Ripple For Figures 6–9, all filter plots apply to a sample rate kHz. The filters scale ...
Page 13
Input Frequency—Hz Figure 10. IIR Receive Filter Response Input Frequency—Hz Figure 11. IIR Receive Filter Passband Ripple For Figures 10–13, all filter plots apply to a sample rate kHz. The filters scale with the sample rate ...
Page 14
Input Frequency—Hz Figure 14. IIR Receive Group Delay 14 Input Frequency—Hz Figure 15. IIR Transmit Group Delay Rev. 1.2 ...
Page 15
Decoupling cap for Ground Plane In DAA Section VCC R3 Decoupling cap for U1 VA C10 10 D3 BAV99 RGDTb OFHKb MCLK MCLK OFHK 2 15 FSYNCb FSYNC RGDT 3 14 ...
Page 16
Bill of Materials Table 13. Component Values—Typical Application 1 Component C1,C4 150 pF, 3 kV, X7R, ±20% C2 Not Installed C3 0. X7R, ±20 µ Tant/Elec, ±20% C6,C10,C16 0.1 ...
Page 17
Analog Output Figure 17 illustrates an optional application circuit to support the analog output capability of the Si3035 for call progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0 dB, –6 ...
Page 18
Functional Description The Si3035 is an integrated chipset that provides a low-cost, isolated, silicon-based interface to the telephone line. The Si3035 saves cost and board area by eliminating the need for a modem AFE or serial ...
Page 19
Fs may be established prior to executing the off-hook, such 10.286 kHz. The delay allows line transients to settle prior to normal use. Ring Detect The ring signal enters the Si3035 through low ...
Page 20
The digital interface consists of a single, synchronous serial link which communicates both telephony and control data. In Serial mode the Si3021 operates as a master, where the master clock (MCLK ...
Page 21
Com m unications Fram e 1 (CF1) FSYNC Prim ary Secondary FC 0 D15–D0 Secondary SDI XMT Data Data Secondary SDO RCV Data Data 16 SCLKS 128 SCLKS 256 SCLKS Figure 20. Hardware FC Secondary Request FSYNC (m ode 0) ...
Page 22
FSYNC (m ode 0) FSYNC (m ode 1) SDI SDO Figure 22. Secondary Communication Data Format—Write Cycle F F UP1 PLL1 DIV N1 MCLK 8 bits PLL1 DIV M1 8 bits Figure 23. Clock Generation Subsystem ...
Page 23
Table 17. N2, M2 Values (CGM = (Hz) N2 7200 2 8000 9 8229 7 8400 6 9000 4 9600 3 10286 7 The main design consideration is the generation of a base frequency, defined as the ...
Page 24
rate, typically 7200 Hz. All further sample rate changes are then made by simply writing to Register 9 to update PLL2. The final design consideration for the clock generator is the update rate of PLL1. The ...
Page 25
AOUT signal can be set to –20 dB, –26 dB, –32 dB, or mute. The receive portion of the AOUT signal can be set to 0 dB, –6 dB, –12 dB, or mute. Figure 17 on page 17 illustrates a ...
Page 26
signalling, the master device will have a unique setting relative to the slave devices. The DSP can use this information to determine which FSYNC marks the beginning of a sequence of data transfers. The delayed frame ...
Page 27
DSP SCLK SDO SDI FSYNC INT0 47 k Figure 25. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem) MCLK Si3021 MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD + Si3000 SCLK MCLK FSYNC SDI SDO Voice ...
Page 28
Master Serial Mode 1 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD ...
Page 29
Master Serial Mode 1 Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1 Serial Mode 2 Slave 1 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary ...
Page 30
Master Serial Mode 0 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD ...
Page 31
DSP SCLK SDO SDI FSYNC INT0 Figure 30. Typical Connection for Multiple Si3035s Rev. 1.2 Si3035 MCLK Si3021–M aster MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD VCC M1 M0 Si3021–Slave 1 MCLK SCLK FSYNC SDI SDO ...
Page 32
Revision Identification The Si3035 provides the system designer the ability to determine the revision of the Si3021 and/or the Si3012. Register 11 identifies the revision of the Si3021 with 4 bits named REVA. Register 13 identifies ...
Page 33
SDI. This data is passed across the isolation barrier, looped from the TX to the RX pin, passed back across the isolation barrier, and presented to the data pump on SDO. To enable this mode, clear ...
Page 34
Control Registers Any register not listed here is reserved and should not be written. Register Name Bit 7 1 Control Control 2 3 Control 3 4 Control 4 5 DAA Control 1 6 ...
Page 35
Register 1. Control 1 Bit Name SR Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables chip for normal operation Sets all registers to their reset value. 6:2 ...
Page 36
Register 3. Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 4. Control 4 Bit Name Type Reset settings = ...
Page 37
Register 5. DAA Control 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 OPOL Off-Hook Polarity Off-hook pin is active low Off-hook pin is active high. ...
Page 38
Register 6. DAA Control 2 Bit Name CPE ATM1 ARM1 PDL Type R/W R/W R/W R/W Reset settings = 0111_0000 Bit Name 7 CPE Charge Pump Enable Charge pump is ...
Page 39
Register 8. PLL1 Multiply M1 Bit Name M1[7:0] Type R/W Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit Name 7:0 M1[7:0] M1 Multiplier. Contains the (value – 1) ...
Page 40
Register 11. Chip Revision Bit Name Type Reset settings = N/A Bit Name 7:4 Reserved Read returns zero. 3:0 REVA[3:0] Chip Revision. Four-bit value indicating the revision of the Si3021 (DSP-side) chip. ...
Page 41
Register 13. Transmit and Receive Gain Bit Name CBID REVB[3:0] Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 CBID Chip B ID Indicates the line side is domestic ...
Page 42
Register 14. Daisy-Chain Control Bit Name NSLV2 NSLV1 NSLV0 SSEL1 SSEL0 Type R/W R/W R/W Reset settings = 0000_0010 (serial mode 0, 1) Reset settings = 0011_1111 (serial mode 2) Bit Name 7:5 ...
Page 43
Register 15.TX/RX Gain Control Bit Name TXM ATX2 ATX1 Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
Page 44
Register 16. IIR Filter Control Bit Name IIRE Type R/W R/W R/W R/W Reset settings = 0000_1000 Bit Name 7:5 Reserved Read returns zero (must always be written with ...
Page 45
A —U L1 950 Although designs using the Si3035 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 31 shows two ...
Page 46
Pin Descriptions: Si3021 Si3021 (SOIC) MCLK 1 FSYNC 2 SCLK SDO 5 SDI 6 FC/RGDT 7 RESET 8 SOIC TSSOP Pin Name Pin # Pin # 1 13 MCLK 2 14 FSYNC ...
Page 47
Table 21. Si3021 Pin Descriptions (Continued) SOIC TSSOP Pin Name Pin # Pin # C1A 12 8 GND RGDT/FSD 16 12 OFHK Description Mode Select 1 ...
Page 48
Pin Descriptions: Si3012 (SOIC or TSSOP) Pin Name Pin # Test Input A. 1 TSTA Allows access to test modes which are reserved for factory use. This pin has an internal pull-up and should be left ...
Page 49
Table 22. Si3012 Pin Descriptions (Continued) (SOIC or TSSOP) Pin Name Pin # Hybrid Node Output. 11 HYBD Balancing capacitor connection used for JATE out-of-band noise support. DC Termination. 12 DCT Provides DC termination to the telephone network. External Resistor. ...
Page 50
... AC Link 50 Table 23. Ordering Guide Digital Line Digital (SOIC) (SOIC) (TSSOP) Si3021-KS Si3014-KS Si3021-KT Si3021-KS Si3012-KS Si3021-KT Si3024-KS Si3012-KS Si3024-KT Si3024-KS Si3014-KS Si3024-KT Si3021-KS Si3015-KS Si3021-BS Si3015-BS Si3025-KS Si3012-KS Si3025-KS Si3014-KS Rev. 1.2 Line Temperature (TSSOP) Si3014-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3012-KT 0° ...
Page 51
SOIC Outline Figure 32 illustrates the package details for the Si3021 and Si3012. Table 24 lists the values for the dimensions shown in the illustration. Figure 32. 16-pin Small Outline Plastic Package (SOIC) Table 24. Package Diagram Dimensions Controlling Dimension: ...
Page 52
TSSOP Outline Figure 33 illustrates the package details for the Si3021 and Si3014. Table 25 lists the values for the dimensions shown in the illustration Figure 33. 16-pin Thin Small Shrink ...
Page 53
Data Sheet Changes from Version 1.0 to Version 1.1 Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 13. The tolerance was also changed from ...
Page 54
Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in ...