EDD5104ADTA-7A-E Elpida Memory, Inc., EDD5104ADTA-7A-E Datasheet
EDD5104ADTA-7A-E
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EDD5104ADTA-7A-E Summary of contents
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... PRELIMINARY DATA SHEET 512M bits DDR SDRAM EDD5104ADTA-E (128M words 4 bits) EDD5108ADTA-E (64M words 8 bits) EDD5116ADTA-E (32M words 16 bits) Description The EDD5104AD, the EDD5108AD EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 2 bits prefetch- pipelined architecture ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Ordering Information Mask Organization Part number version (words EDD5104ADTA-6B-E EDD5104ADTA-7A-E D 128M EDD5104ADTA-7B-E EDD5108ADTA-6B-E EDD5108ADTA-7A-E 64M EDD5108ADTA-7B-E EDD5116ADTA-6B-E EDD5116ADTA-7A-E 32M EDD5116ADTA-7B-E EDD5104ADTA-6BL-E EDD5104ADTA-7AL-E D 128M EDD5104ADTA-7BL-E EDD5108ADTA-6BL-E EDD5108ADTA-7AL-E 64M EDD5108ADTA-7BL-E EDD5116ADTA-6BL-E EDD5116ADTA-7AL-E 32M EDD5116ADTA-7BL-E Part Number ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................10 Pin Function.................................................................................................................................................11 Command Operation ...................................................................................................................................13 Simplified State Diagram .............................................................................................................................20 Operation of the DDR SDRAM ....................................................................................................................21 Timing Waveforms.......................................................................................................................................40 Package Drawing ........................................................................................................................................46 Recommended Soldering Conditions..........................................................................................................47 Preliminary Data Sheet E0501E10 (Ver. 1.0) 3 ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Electrical Specifications All voltages are referenced to VSS (GND). After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E DC Characteristics 1 ( +70 C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Parameter Symbol Grade Operating current (ACT- -6B IDD0 PRE) -7A, -7B Operating current -6B IDD1 (ACT-READ-PRE) -7A, -7B Idle power down standby IDD2P current Floating idle standby -6B IDD2F current -7A, -7B Quiet idle standby current IDD2Q ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V) Parameter Symbol Input capacitance CI1 CI2 Delta input capacitance Cdi1 Cdi2 Data input/output capacitance CI/O Delta input/output capacitance Cdio Notes: 1. These parameters are measured on conditions + DOUT circuits are disabled. AC Characteristics ( +70 C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Parameter Symbol Address and control input pulse width tIPW Mode register set command cycle tMRD time Active to Precharge command period tRAS Active to Active/Auto refresh tRC command period Auto refresh to Active/Auto refresh tRFC command period Active to Read/Write delay tRCD ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Test Conditions Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate CK VID /CK Measurement point Preliminary Data Sheet E0501E10 (Ver. 1.0) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Timing Parameter Measured in Clock Cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay ( (CL = 2.5) Burst stop command to DQ High ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Block Diagram CK /CK CKE A0 to A12, BA0, BA1 Mode register /CS /RAS /CAS /WE Preliminary Data Sheet E0501E10 (Ver. 1.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Pin Function CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write access ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Command Operation Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal. Command Ignore command No operation Burst stop in read command Column address and read command ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Current state /CS /RAS /CAS /WE 1 Precharging ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Current state /CS /RAS /CAS /WE 6 Read Read with auto-pre charge ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Current state /CS /RAS /CAS /WE Write with auto pre-charge Remark: H: VIH. L: VIL. : VIH or VIL Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Command Truth Table for CKE Current State CKE n – /CS /RAS /CAS /WE Address Self refresh Self refresh recovery ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 s. The output buffer becomes High-Z after auto- refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Simplified State Diagram MODE REGISTER SET ACTIVE POWER DOWN WRITE Write WRITE WRITE WITH AP WRITEA POWER POWER APPLIED ON PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Operation of the DDR SDRAM Power-up Sequence (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E BA0 BA1 A12 A11 A10 EMRS Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out. Burst length = 2 Starting Ad. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E t0 t0.5 CK /CK Command READ tRPRE DQS DQS CL = 2.5 DQ Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to ‘ ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Command Intervals A Read command to the consecutive Read command Interval Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE t0 CK /CK Command ACT NOP Row Column A Address BA DQ ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA /CK Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active READ to READ Command Interval (different bank) Preliminary Data Sheet E0501E10 (Ver. 1. READ READ NOP Column A Column B out out A0 A1 Column = A Column = B ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Write command to the consecutive Write command Interval Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command ACT NOP WRIT Row Column A Address BA DQ ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA /CK Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E0501E10 (Ver. 1.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Read command to the consecutive Write command interval with the BST command Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command READ BST NOP ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Write command to the consecutive Read command interval: To complete the burst operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command WRIT BL cycle DM DQ ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Write command to the consecutive Read command interval: To interrupt the write operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA /CK Command WRIT NOP READ 2 cycle DM in0 in1 DQ DQS Data masked [WRITE to READ delay = 2 clock cycle /CK Command WRIT NOP 3 cycle DM DQ in0 in1 DQS Data masked Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued /CK Command ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command /CK Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command /CK Command WRIT DM DQS DQ in0 in1 WRITE to PRECHARGE Command Interval (same bank) ( Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Bank active command interval Destination row of the consecutive ACT command Bank Row address address State 1. Same Any ACTIVE 2. Different Any ACTIVE IDLE CK /CK Command ACTV ACT Address ROW Bank0 Active tRRD Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E DM Control DM can mask input data products, UDM and LDM can mask the upper and lower byte of input data respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Timing Waveforms Command and Addresses Input Timing Definition CK /CK Command (/RAS, /CAS, /WE, /CS) Address Read Timing Definition tCK /CK CK tCH tCL tRPRE DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) tDS DM tDS Preliminary Data Sheet E0501E10 (Ver. 1.0) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Read Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active Preliminary Data Sheet E0501E10 (Ver. 1.0) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Write Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH tIS tIH /CS tIS tIH tIS tIH /RAS tIS tIH tIS tIH /CAS tIS tIH tIS tIH /WE tIS tIH tIS tIH BA tIS tIH tIS tIH A10 tIS tIH ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Mode Register Set Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA code Address valid code DM High-Z DQS High-Z DQ (output) tRP Mode Precharge register If needed set Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a C:a DM DQS DQ (output) High-Z DQ (input) ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Preliminary Data Sheet E0501E10 (Ver. 1. High-Z tRFC Auto Bank 0 Refresh Active Bank 0 Read VIH or VIL ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Self Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Preliminary Data Sheet E0501E10 (Ver. 1.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Package Drawing 66-pin Plastic TSOP (II) Solder plating: Lead free (Sn-Bi 22.22 ± 0. PIN 0.65 0.17 to 0.32 0. 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD51XXADTA. Type of Surface Mount Device EDD51XXADTA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) > Preliminary Data Sheet E0501E10 (Ver. 1.0) 47 ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred ...
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... EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc ...