EM636165TS-7G Etron Technology Inc., EM636165TS-7G Datasheet
EM636165TS-7G
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EM636165TS-7G Summary of contents
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... Row Cycle time(min.) RC Ordering Information Part Number EM636165TS/VE-55G EM636165TS/VE-6G EM636165TS/VE-7G EM636165TS/VE-7LG TS : indicates TSOP II package VE : indicates VFBGA package L: indicates Low Power G: indicates Pb and Halogen Free for TSOPII Package ndicates Pb Free for VFBGA Package i Etron Technology, Inc. No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 Etron Technology, Inc ...
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Pin Assignment (TSOP II Top View) 1 VDD DQ0 2 DQ1 3 VSSQ 4 5 DQ2 DQ3 6 VDDQ 7 DQ4 8 DQ5 9 10 VSSQ DQ6 11 DQ7 12 VDDQ 13 14 LDQM 15 WE# CAS# 16 RAS# 17 ...
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Block Diagram CLOCK CLK BUFFER CKE CS# RAS# COMMAND CAS# DECODER WE# COLUMN A10/AP COUNTER A0 ADDRESS BUFFER A9 A11 REFRESH COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER 3 EM636165 2048x256 x 16 CELL ARRAY (BANK #0) Column Decoder DQ0 DQs ...
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Pin Descriptions Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input ...
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LDQM, Input Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when UDQM LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during ...
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Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode ...
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Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", A11 = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BA signals. By latching the row address A10 ...
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CLK COMMAND CAS# latency=2 t DQ’s CK2, CAS# latency=3 t DQ’s CK3, Burst Read Operation The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e. LDQM/UDQM latency is two clocks for ...
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T0 CLK DQM COMMAND NOP CAS# latency=2 ’ CK2, Read to Write Interval T0 T1 CLK DQM COMMAND NOP READ A ’ Read to Write Interval T0 CLK DQM COMMAND NOP CAS# latency=2 ’ t ...
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T0 CLK Bank, ADDRESS Col A READ A COMMAND CAS# latency=2 ’ CK2, CAS# latency=3 ’ CK3, 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, ...
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T0 CLK NOP COMMAND ’ Write Interrupted by a Write The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is ...
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CLK DQM WRITE COMMAND ADDRESS DQ Note: The LDQM/UDQM can remain low in this example if the length of the write burst Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# ...
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T0 T1 CLK CKE CS# RAS# CAS# WE# A11 A10 A0-A9 DQM DQ Hi-Z Mode Register Set Cycle The mode register is divided into various fields depending on functionality. Address A11,10 Function RFU* *Note: RFU (Reserved for future use) should ...
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Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length full page, but Interleave Mode only supports burst length ...
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Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation • Write Burst Length (A9) This bit is ...
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T0 CLK NOP COMMAND CAS# latency=2,3 ’ CK1, Termination of a Burst Write Operation 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address ...
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Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE = "L") When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle ...
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Absolute Maximum Rating Symbol Item Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature A T Storage Temperature STG P Power Dissipation D I Short Circuit Output Current OUT Recommended ...
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Recommended D.C. Operating Conditions Description/Test condition Operating Current ≥ (min), Outputs Open RC RC One bank active Precharge Standby Current in non-power down mode = 15ns, CS# ≥ V (min), CKE ≥ Input signals ...
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Electrical Characteristics and Recommended A.C. Operating Conditions = 3.3V ± 0.3V 0~70 ° C) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD ...
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A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals Output 30pF LVTTL D.C. Test Load (A) 7. Transition times are ...
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Timing Waveforms Figure 1. AC Parameters for Write Timing T10 CLK CKE CS# RAS# CAS# WE# A11 t ...
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Figure 2. AC Parameters for Read Timing CLK CKE t IS CS# RAS# CAS# WE# A11 A10 RAx t IS A0-A9 RAx DQM Hi-Z DQ Activate Command Bank A Etron Confidential (Burst ...
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Figure 3. Auto Refresh (CBR T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 A0- DQM DQ Precharge All Auto Refresh Command Command Etron Confidential (Burst ...
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Figure 4. Power on Sequene and Auto Refresh (CBR T10 CLK t CK CKE High Level is reauired CS# RAS# CAS# WE# A11 A10 Address Key A0-A9 DQM t RP ...
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Figure 5. Self Refresh Entry & Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# *Note 8 RAS# CAS# A11 A0-A9 WE# DQM Hi-Z DQ Self Refresh Enter Note: To Enter SelfRefresh Mode ...
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Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx DQM Hi-Z ...
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Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx DQM Hi-Z ...
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Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx DQM Hi-Z ...
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Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx DQM Hi-Z ...
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Figure 8. Power Down Mode and Clock Mask T10 CLK CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx DQM Hi-Z DQ ACTIVE ...
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Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAw RAx A0-A9 RAw CAw DQM ...
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Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAw A0-A9 RAw CAw DQM ...
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Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RBw A0-A9 RBw CBw DQM ...
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Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RBw A0-A9 RBw CBw DQM ...
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Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RBx A0-A9 RBx CBx ...
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Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RBx A0-A9 RBx CBx t RCD DQM ...
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Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx t RCD DQM ...
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Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx t RCD DQM ...
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Figure 13.1. Read and Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAx A0-A9 RAx CAx DQM Hi-Z DQ Ax0 Activate Read Cammand Command ...
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Figure 13.2. Read and Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAx A0-A9 RAx CAx DQM Hi-Z DQ Activate Read Cammand Command Bank ...
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Figure 14.1. Interleaving Column Read Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RAx A0-A9 RAx CAy RAx RCD DQM Hi-Z ...
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Figure 14.2. Interleaved Column Read Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RBx RAx RAx A0-A9 RAx CAx RBx t RCD DQM Hi-Z DQ Activate ...
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Figure 15.1. Interleaved Column Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBw A0-A9 RAx CAx RBw t RCD DQM t RRD Hi-Z ...
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Figure 15.2. Interleaved Column Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RBw RAx RAx A0-A9 RAx CAx RBw t RCD DQM t >t RCD ...
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Figure 16.1. Auto Precharge after Read Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ Ax0 ...
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Figure 16.2. Auto Precharge after Read Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ Activate ...
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Figure 17.1. Auto Precharge after Write Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ DAx0 ...
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Figure 17.2. Auto Precharge after Write Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ DAx0 ...
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Figure 18.1. Full Page Read Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 RAx CAx RBx DQM Hi Activate Read ...
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Figure 18.2. Full Page Read Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ Activate Read Activate ...
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Figure 19.1. Full Page Write Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ DAx DAx+1 DAx+2 ...
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Figure 19.2. Full Page Write Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 RAx CAx RBx DQM Hi-Z DQ DAx DAx+1 DAx+2 ...
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Figure 20. Byte Write Operation T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx CAx LDQM UDQM DQ0-DQ7 Ax0 DQ8-DQ15 Activate Read Upper Bytes ...
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Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= T10 CLK t CK High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS# RAS# CAS# ...
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Figure 22. Full Page Random Column Read T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RBx RAx A0-A9 RAx RBx CAx DQM t t RCD RRD ...
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Figure 23. Full Page Random Column Write T10 CLK t CK CKE CS# RAS# CAS# WE# A11 A10 RAx RAx RBx A0-A9 RAx RBx CAx DQM t t RRD RCD ...
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Figure 24. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 RAx ...
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Pin TSOP II Package Outline Drawing Information Symbol Dimension in inch Min Normal － A 0.002 A1 0.035 A2 0.008 B － c 0.82 D 0.395 E － e 0.455 HE 0.016 L ...
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Units in mm TOP VIEW A1 CORNER 1.00 MAX SEATING PLANE Etron Confidential ...