OR2T15A-6S208 List of Unclassifed Manufacturers, OR2T15A-6S208 Datasheet
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OR2T15A-6S208
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OR2T15A-6S208 Summary of contents
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... OR2C06A/OR2T06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A/OR2T12A OR2C15A/OR2T15A/OR2T15B OR2C26A/OR2T26A OR2C40A/OR2T40A/OR2T40B * The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The second number assumes 30 design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing RAM (or 256 gates) per PFU ...
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ORCA Series 2 FPGAs Contents Features ...................................................................... 1 Description................................................................... 3 ORCA Foundry Development System Overview......... 5 Architecture ................................................................. 5 Programmable Logic Cells .......................................... 5 Programmable Function Unit ................................... 5 Look-Up Table Operating Modes ............................ 7 Latches/Flip-Flops ................................................. 15 PLC Routing ...
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Data Sheet June 1999 Description The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the ...
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ORCA Series 2 FPGAs Description (continued) The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/configura- tion circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several ...
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Data Sheet June 1999 ORCA Development System Foundry Overview The ORCA Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the ...
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ORCA Series 2 FPGAs Programmable Logic Cells CARRY QLUT3 CARRY QLUT2 CARRY QLUT1 CARRY QLUT0 B1 B0 ...
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Data Sheet June 1999 Programmable Logic Cells Table 3 lists the basic operating modes of the LUT. The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, ...
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ORCA Series 2 FPGAs Programmable Logic Cells The LUT ripple mode operation offers standard arith- metic functions, such as 4-bit adders, subtractors, adder/subtractors, and counters. In the ORCA Series 2, there are two new ripple modes available. The first new ...
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Data Sheet June 1999 Programmable Logic Cells F5M and F5X Modes—Special Function Modes The PFU contains logic to implement two special func- tion modes which are variations on the F5 mode. As with the F5 mode, the LUT implements two ...
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ORCA Series 2 FPGAs Programmable Logic Cells QLUT3 QLUT2 QLUT1 QLUT0 B0 B0 Figure 8. F5M Mode—One Six-Input Variable Function F5M ...
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Data Sheet June 1999 Programmable Logic Cells The second submode is the counter submode (see Figure 10). The present count is supplied to input A[3:0], and then output F[3:0] will either be incre- mented by one for an up counter ...
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ORCA Series 2 FPGAs Programmable Logic Cells Asynchronous Memory Modes—MA and MB The LUT in the PFU can be configured as either read/ write or read-only memory. A read/write address (A[3:0], B[3:0]), write data (WD[1:0], WD[3:2]), and two write-enable (WE) ...
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Data Sheet June 1999 Programmable Logic Cells Synchronous Memory Modes—SSPM and SDPM The MA/MB asynchronous memory modes described previously allow the PFU to perform (64 bits) single-port RAM. Synchronously writing to this RAM requires the ...
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ORCA Series 2 FPGAs Programmable Logic Cells UPPER ADDRESS BITS UPPER ADDRESS BITS Note: The lower address bits are not shown. Figure 16. Synchronous RAM with Write-Port Enable (WPE) To increase memory word depth above 16 (e.g 4), ...
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Data Sheet June 1999 Programmable Logic Cells A4 WE WRITE PULSE D Q GENERATOR CIN, C0 WPE D Q WA[3:0] A[3: WD[1:0] WD[1: RA[3:0] B[3:0] Figure 17. SDPM Mode— Synchronous Dual-Port Memory The Series ...
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ORCA Series 2 FPGAs Programmable Logic Cells The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the global set/reset (GSRN) or local set/reset (LSR) are inactive, the storage element operates normally as ...
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Data Sheet June 1999 Programmable Logic Cells PLC Routing Resources Generally, the ORCA Foundry Development System is used to automatically route interconnections. Interac- tive routing with the ORCA Foundry design editor (EPIC) is also available for design optimization. To use ...
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ORCA Series 2 FPGAs Programmable Logic Cells TRI BIDI CONTROLLER BIDIH CONTROLLER Figure 20. 3-Statable Bidirectional Buffers Intra-PLC Routing The function of the intra-PLC routing resources is to connect the PFU’s input and output ports to the routing resources used ...
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Data Sheet June 1999 Programmable Logic Cells Inter-PLC Routing Resources The inter-PLC routing is used to route signals between PLCs. The lines occur in groups of four, and differ in the numbers of PLCs spanned. The X1 lines span one ...
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ORCA Series 2 FPGAs Programmable Logic Cells XL Lines. The long XL lines run vertically and horizon- tally the height and width of the array, respectively. There are a total of eight XL lines per PLC: four hori- zontal (HXL[3:0]) ...
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Data Sheet June 1999 Programmable Logic Cells HX4[7] HX4[6] HX4[5] HX4[4] HX1[7:4] CKL CKR PFU HXL[3] HXL[2] HXL[1] HXL[0] HXH[3:0] HX1[3:0] HX4[3] HX4[2] HX4[1] HX4[0] HX4[7] HX4[6] HX4[5] HX4[4] HX1[7:4] CKL CKR PFU HXL[3] HXL[2] HXL[1] HXL[0] HXH[3:0] HX1[3:0] HX4[3] ...
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ORCA Series 2 FPGAs Programmable Logic Cells PLC Architectural Description Figure architectural drawing of the PLC which reflects the PFU, the lines, and the CIPs. A discussion of each of the letters in the drawing follows. A. ...
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Data Sheet June 1999 Programmable Logic Cells VX4[0] VX4[1] VX4[2] VX4[3] VX1[0] VX1[1] VX1[2] VX1[3] CKT CKB GSRN INT[0] INT[1] INT[2] INT[3] INT[4] CARRY_T VXL[0] VXL[1] VXL[2] VXL[3] VXH[0] VXH[1] VXH[2] VXH[3] VX1[4] VX1[5] VX1[6] VX1[7] VX4[4] VX4[5] VX4[6] VX4[7] ...
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ORCA Series 2 FPGAs Programmable Logic Cells J. Any five of the eight output signals can be routed out of the PLC. The eight signals are the four LUT out- puts (F0, F1, F2, and F3) and the four latch/FF ...
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Data Sheet June 1999 Programmable Input/Output Cells The programmable input/output cells (PICs) are located along the perimeter of the device. Each PIC interfaces to four bond pads and contains the neces- sary routing resources to provide an interface between I/O ...
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ORCA Series 2 FPGAs Programmable Input/Output Cells (continued PULL-UP DELAY TTL/CMOS POLARITY PAD SLEW RATE PULL-DOWN A. Simplified Diagram of OR2CxxA Programmable I/O Cell (PIC PULL-UP DELAY POLARITY PAD SLEW RATE PULL-DOWN B. Simplified Diagram of ...
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Data Sheet June 1999 Programmable Input/Output Cells (continued) Regardless of the power supply that the V connected 3.3 V), the OR2TxxA devices will drive the pin to the 3.3 V levels when the output buffer is ...
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ORCA Series 2 FPGAs Programmable Input/Output Cells (continued) PIC Routing Resources The PIC routing is designed to route 4-bit wide buses efficiently. For example, any four consecutive I/O pads can have both their input and output signals routed into one ...
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Data Sheet June 1999 Programmable Input/Output Cells (continued) PIC Architectural Description The PIC architecture given in Figure 26 is described using the following letter references. The figure depicts a PIC at the top of the array, so inter-PIC routing is ...
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ORCA Series 2 FPGAs Programmable Input/Output Cells K PXL[1] A PXL[0] PXH[0] PXH[1] B PXH[2] PXH[3] PX2[2] PX2[3] C PX2[0] PX2[1] M PX1[0] PX1[1] D PX1[2] PX1[ PLC-PIC Routing Resources There is no direct connection between ...
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Data Sheet June 1999 Programmable Input/Output Cells (continued) Figure 27 shows paths to and from pads and the use of MUX CIPs to connect lines. Detail A shows six MUX CIPs for the pad P0 used to construct the net ...
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ORCA Series 2 FPGAs Interquad Routing In all the ORCA Series 2 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing has been added to route signals between the quadrants, especially to the quadrant ...
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Data Sheet June 1999 Interquad Routing (continued) In the hIQ block in Figure 29, the XH lines from one quadrant connect through a CIP to its counterpart in the opposite quadrant, creating a path that spans the PLC array. Since ...
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ORCA Series 2 FPGAs Interquad Routing (continued) Subquad Routing (OR2C40A/OR2T40A Only) In the ORCA OR2C40A/OR2T40A/OR2T40B, each quadrant of the device is split into smaller arrays of PLCs called subquads. Each of these subquads is made ...
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Data Sheet June 1999 Interquad Routing (continued) HSUB[11] HSUB[10] HSUB[9] HSUB[8] HSUB[7] HSUB[6] HSUB[5] HSUB[4] HSUB[3] HSUB[2] HSUB[1] HSUB[0] Figure 31. Horizontal Subquad Routing Connectivity The X4 and XH lines make the only connections to the subquad lines; therefore, the ...
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ORCA Series 2 FPGAs Interquad Routing (continued) PIC Interquad (MID) Routing Between the PICs in each quadrant, there is also con- nectivity between the PIC routing and the interquad routing. These blocks are called LMID (left), TMID (top), RMID (right), ...
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Data Sheet June 1999 Programmable Corner Cells Programmable Routing The programmable corner cell (PCC) contains the cir- cuitry to connect the routing of the two PICs in each corner of the device. The PIC PX1 and PX2 lines are directly ...
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ORCA Series 2 FPGAs Clock Distribution Network SEE DETAIL A CLK PIN CLOCK SPINE PIC PT8 PLC R1C8 PLC R18C8 DETAIL A HCK HCK R7C7 R7C8 HXL CLOCK CLOCK BRANCH ...
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Data Sheet June 1999 Clock Distribution Network Alternatively, the clock can be routed from the spine to the branches by using the BIDIs instead of the long-line drivers. This results in added delay in the clock net, but the clock ...
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ORCA Series 2 FPGAs FPGA States of Operation Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration, and start-up. Figure 36 outlines these three FPGA states. POWERUP – POWER-ON TIME DELAY INITIALIZATION – CLEAR ...
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Data Sheet June 1999 FPGA States of Operation V DD RESET PRGM INIT M[3:0] CCLK HDC LDC DONE USER I/O INTERNAL RESET (gsm) Figure 37. Initialization/Configuration/Start-Up Waveforms All OR2CxxA I/Os operate as TTL inputs during config- uration (OR2TxxA/OR2TxxB I/Os are ...
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ORCA Series 2 FPGAs FPGA States of Operation Start-Up After configuration, the FPGA enters the start-up phase. This phase is the transition between the config- uration and operational states and begins when the number of CCLKs received after INIT to ...
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Data Sheet June 1999 FPGA States of Operation ATT3000 F DONE I/O GLOBAL RESET ORCA CCLK_NOSYNC DONE I GSRN ACTIVE ORCA CCLK_SYNC DONE IN DONE C1, C2, C3 I/O ...
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ORCA Series 2 FPGAs Configuration Data Format Using ORCA Foundry to Generate Configuration RAM Data The configuration data defines the I/O functionality, logic, and interconnections. The bit stream is gener- ated by the development system. The bit stream cre- ated ...
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... The data frames for all the Series 2 series devices are given in Table 8. An alignment field is required in the slave parallel mode for the uncompressed format. The alignment field (shown by [A series of 0s: five for the OR2C06A/OR2T06A, OR2C10A/OR2T10A, OR2C15A/OR2T15A/OR2T15B, and OR2C26A/OR2T26A; three for the OR2C40A/OR2T40A/OR2T40B; and one for the OR2C04A/OR2T04A, OR2C08A/OR2T08A, and OR2C12A/ OR2T12A ...
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ORCA Series 2 FPGAs Configuration Data Format Table 9. Configuration Frame Format and Contents 11111111 0010 Header 24-Bit Length Count Configuration frame length 1111 0 P—1 C—0 Opar, Epar ID Frame Addr[10:0] = (Optional) 11111111111 Prty_En Reserved [42:0] ID 111 ...
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Data Sheet June 1999 Bit Stream Error Checking There are three different types of bit stream error checking performed in the ORCA Series 2 FPGAs: ID frame, frame alignment, and parity checking. An optional ID data frame can be sent ...
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ORCA Series 2 FPGAs FPGA Configuration Modes Master Serial Mode In the master serial mode, the FPGA loads the configu- ration data from an external serial ROM. The configura- tion data is either loaded automatically at start- ...
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Data Sheet June 1999 FPGA Configuration Modes Asynchronous Peripheral Mode Figure 42 shows the connections needed for the asyn- chronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessor- peripheral interface. The microprocessor ...
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ORCA Series 2 FPGAs FPGA Configuration Modes Slave Serial Mode The slave serial mode is primarily used when multiple FPGAs are configured in a daisy chain. The serial slave serial mode is also used on the FPGA evaluation board which ...
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Data Sheet June 1999 FPGA Configuration Modes Daisy Chain Multiple FPGAs can be configured by using a daisy chain of the FPGAs. Daisy chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead ...
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ORCA Series 2 FPGAs Special Function Blocks Special function blocks in the Series 2 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners of the FPGA array. Single Function Blocks Most of the special function blocks ...
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Data Sheet June 1999 Special Function Blocks Global 3-State Control (TS_ALL) The TS_ALL block resides in the upper-right corner of the FPGA array. To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. ...
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ORCA Series 2 FPGAs Special Function Blocks Boundary Scan The increasing complexity of integrated circuits (ICs) and IC packages has increased the difficulty of testing printed-circuit boards (PCBs). To address this testing problem, the IEEE standard 1149.1 - 1990 ( ...
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Data Sheet June 1999 Special Function Blocks CCLK A[17:0] A[17:0] EPROM SERIES D[7:0] D[7:0] MASTER OE DONE CE PRGM PROGRAM GND M0 The BSM also increases test throughput with a dedi- cated automatic ...
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ORCA Series 2 FPGAs Special Function Blocks There are four ORCA -defined instructions. The PLC scan rings 1 and 2 (PSR1, PSR2) allow user-defined internal scan paths using the PLC latches/FFs. The RAM_Write Enable (RAM_W) instruction allows the user to ...
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Data Sheet June 1999 Special Function Blocks ORCA Series TAP Controller (TAPC) The ORCA Series TAP controller (TAPC 1149.1 compatible test access port controller. The 16 JTAG state assignments from the IEEE 1149.1 specification are used. The TAPC ...
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ORCA Series 2 FPGAs Special Function Blocks Boundary-Scan Cells Figure diagram of the boundary-scan cell (BSC) in the ORCA series PICs. There are four BSCs in each PIC: one for each pad, except as noted above. The ...
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Data Sheet June 1999 Special Function Blocks TCK TMS TDI Figure 52. Instruction Register Scan Timing Diagram Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising ...
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ORCA Series 2 FPGAs ORCA Timing Characteristics To define speed grades, the ORCA Series part number designation (see Table 54) uses a single-digit number to designate a speed grade. This number is not related to any single ac parameter. Higher ...
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Data Sheet June 1999 ORCA Timing Characteristics (continued) Table 15B. Derating for Commercial/Industrial Devices (OR2TxxB) Power Supply Voltage T J (°C) 3.0 V 3.15 V 3.3 V –40 0.81 0.78 0.76 0 0.86 0.83 0.80 25 0.9 0.87 0.83 85 ...
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ORCA Series 2 FPGAs Estimating Power Dissipation OR2C06A Clock Power P = [0.63 mW/MHz + (0.25 mW/MHz – Branch) (# Branches) + (0.022 mW/MHz – PFU) (# PFUs) + (0.006 mW/MHz – SMEM_PFU) (# SMEM_PFUs)] fCLK For a quick estimate, ...
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Data Sheet June 1999 Estimating Power Dissipation P = [0.69 mW/MHz + (0.38 mW/MHz – Branch) CLK (20 Branches) + (0.022 mW/MHz – PFU) (150 PFUs) + (0.006 mW/MHz – SMEM_PFU) (16 SMEM_PFUs)] [40 MHz] = 427 ...
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... P where the unit for example of estimating power dissipation, suppose that a fully utilized OR2T15A has an average of three outputs for each of the 400 PFUs, that all 20 clock branches are used, that 150 of the 400 PFUs have FFs clocked at 40 MHz (16 of which are operating in a synchronous memory mode), and that the PFU outputs have an average activity factor of 20% ...
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Data Sheet June 1999 Estimating Power Dissipation OR2T15B and OR2T40B The total operating power dissipated is estimated by summing the standby (I ), internal, and external DDSB power dissipated. The internal and external power is the power consumed in the ...
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ORCA Series 2 FPGAs Pin Information Pin Descriptions This section describes the pins found on the Series 2 FPGAs. Any pin not described in this table is a user-program- mable I/O. During configuration, the user-programmable I/Os are 3-stated with an ...
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Data Sheet June 1999 Pin Information (continued) Table 17. Pin Descriptions (continued) Symbol I/O Special-Purpose Pins Special-Purpose Pins (Become User I/O After Configuration) (continued) M0, M1 During powerup and initialization, M0—M2 are used to select the configuration mode ...
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ORCA Series 2 FPGAs Pin Information (continued) Package Compatibility The package pinouts are consistent across ORCA Series FPGAs with the following exception: some user I/O pins that do not have any special functions will be converted pins ...
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... DD OR2T10A User I/Os 62 — — — DD OR2T12A User I/Os 62 — — — DD OR2T15A User I/Os 62 — — — DD OR2T26A User I/Os — — — — — — DD OR2T40A User I/Os — — ...
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ORCA Series 2 FPGAs Pin Information (continued) Compatibility with Series 3 FPGAs Pinouts for the OR2CxxA, OR2TxxA, and OR2TxxB devices will be consistent with the Series 3 FPGAs for all devices offered in the same packages. This includes the following ...
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Data Sheet June 1999 Pin Information (continued) Table 19. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A 84-Pin PLCC Pinout 2C/2T04A 2C/2T06A Pin Pad Pad PT5A PT6A PT4D PT5D ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 19. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A 84-Pin PLCC Pinout (continued) 2C/2T04A 2C/2T06A Pin Pad Pad PB6A PB7A PB7A ...
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Data Sheet June 1999 Pin Information (continued) Table 20. OR2C/2T04A and OR2C/2T06A 100-Pin TQFP Pinout 2C/2T04A 2C/2T06A Pin Pad Pad PL1C PL1A 4 PL1A PL2A 5 PL2D PL3D 6 ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 20. OR2C/2T04A and OR2C/2T06A 100-Pin TQFP Pinout (continued) 2C/2T04A 2C/2T06A Pin Pad Pad 85 PT7A PT8A 86 PT6D PT7D 87 PT6A PT7A PT5A PT6A 90 V ...
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Data Sheet June 1999 Pin Information (continued) Table 21. OR2C/2T04A and OR2C/2T06A 144-Pin TQFP Pinout 2C/2T04A 2C/2T06A Pin Pad Pad PL1C PL1A 4 PL1B PL2D 5 PL1A PL2A 6 ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 21. OR2C/2T04A and OR2C/2T06A 144-Pin TQFP Pinout (continued) 2C/2T04A 2C/2T06A Pin Pad Pad 85 PR7A PR8A 86 PR7D PR8D PR6A PR7A 89 PR6C PR7C 90 PR6D ...
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Data Sheet June 1999 Pin Information (continued) Table 22. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout Pin 2C/2T04A Pad 2C/2T06A Pad PL1D 4 PL1C 5 PL1B 6 PL1A 7 PL2D 8 PL2C ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 22. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued) Pin 2C/2T04A Pad 2C/2T06A Pad PB1A 44 PB1B 45 PB1C 46 PB1D 47 PB2A 48 ...
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Data Sheet June 1999 Pin Information (continued) Table 22. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued) Pin 2C/2T04A Pad 2C/2T06A Pad 82 RESET 83 PRGM 84 PR10A 85 PR10B 86 PR10C 87 PR10D 88 PR9A 89 PR9B 90 ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 22. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued) Pin 2C/2T04A Pad 2C/2T06A Pad 123 PT10D 124 PT10C 125 PT10B 126 PT10A 127 PT9D 128 PT9C 129 PT9B 130 PT9A 131 ...
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Data Sheet June 1999 Pin Information (continued) Table 23. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout 2C/2T04A 2C/2T06A 2C/2T08A Pin Pad Pad Pad 1 VSS VSS VSS 2 VSS VSS VSS 3 PL1D PL1D PL1D ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 23. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued) 2C/2T04A 2C/2T06A 2C/2T08A Pin Pad Pad Pad 44 PL9A PL10A PL11A 45 See Note PL11D PL12D 46 PL10D ...
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Data Sheet June 1999 Pin Information (continued) Table 23. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued) 2C/2T04A 2C/2T06A 2C/2T08A Pin Pad Pad Pad 87 PB7C PB8C PB9C 88 PB7D PB8D PB9D 89 PB8A PB9A ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 23. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued) 2C/2T04A 2C/2T06A 2C/2T08A Pin Pad Pad Pad 130 VDD VDD VDD 131 PR5A PR6A PR7A 132 PR5B PR6B ...
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Data Sheet June 1999 Pin Information (continued) Table 23. OR2C/2T04A, OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued) 2C/2T04A 2C/2T06A 2C/2T08A Pin Pad Pad Pad 173 PT7D PT8D PT9D 174 PT7C PT8C PT9C 175 PT7B PT8B ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout 2C/2T06A 2C/2T08A Pin Pad Pad PL1D PL1D 4 PL1C ...
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Data Sheet June 1999 Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued) 2C/2T06A 2C/2T08A 2C/2T10A Pin Pad Pad 43 PL9A PL10A PL10D PL11D 46 PL10C ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued) 2C/2T06A 2C/2T08A Pin Pad Pad PB6A PB7A 87 PB6B PB7B 88 PB6C PB7C ...
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Data Sheet June 1999 Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued) 2C/2T06A 2C/2T08A 2C/2T10A Pin Pad Pad 127 PR12D PR13D 128 129 PR11A PR12A 130 PR11B ...
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ORCA Series 2 FPGAs Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued) 2C/2T06A 2C/2T08A Pin Pad Pad 169 PR3D PR4D 170 PR2A PR3A 171 PR2B PR3B 172 PR2C PR3C 173 PR2D ...
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Data Sheet June 1999 Pin Information (continued) Table 24. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued) 2C/2T06A 2C/2T08A 2C/2T10A Pin Pad Pad 211 212 PT6D PT7D 213 PT6C PT7C 214 PT6B ...
Page 92
ORCA Series 2 FPGAs Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout Pin 2C/2T06A Pad 2C/2T08A Pad C2 PL1D PL1D D2 PL1C PL1B D3 PL1B PL1A E4 PL1A PL2D C1 — PL2C D1 — ...
Page 93
Data Sheet June 1999 Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad P3 PL10D PL11D R2 PL10C PL11C T1 PL10B PL11B P4 PL10A PL11A R3 PL11D PL12D T2 ...
Page 94
ORCA Series 2 FPGAs Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad W10 PB6A PB7A V10 PB6B PB7B Y10 PB6C PB7C Y11 PB6D PB7D W11 PB7A PB8A V11 ...
Page 95
Data Sheet June 1999 Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad U20 PR12B PR13B T18 PR12C PR13C T19 PR12D PR13D T20 PR11A PR12A R18 PR11B PR12B P17 ...
Page 96
ORCA Series 2 FPGAs Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad E19 PR2B PR3B D20 PR2C PR3C E18 PR2D PR3D D19 PR1A PR2A C20 PR1B PR2B E17 ...
Page 97
Data Sheet June 1999 Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad B10 PT6D PT7D C10 PT6C PT7C D10 PT6B PT7B A9 PT6A PT7A B9 PT5D PT6D C9 ...
Page 98
ORCA Series 2 FPGAs Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad U13 U17 ...
Page 99
Data Sheet June 1999 Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout Pin 2C12A Pad 2C15A Pad PL1D 5 PL1C 6 PL1B 7 PL1A 8 ...
Page 100
ORCA Series 2 FPGAs Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 45 PL11D 46 PL11C 47 PL11B 48 PL11A 49 PL12D 50 PL12C 51 PL12B 52 PL12A ...
Page 101
Data Sheet June 1999 Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 2C15A Pad 90 PB3D 91 PB4A 92 PB4D 93 PB5A 94 PB5B 95 PB5C 96 PB5D 97 PB6A 98 ...
Page 102
ORCA Series 2 FPGAs Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 135 PB14B 136 PB14D 137 PB15A 138 PB15D 139 PB16A 140 PB16D 141 V SS 142 PB17A 143 PB17B ...
Page 103
Data Sheet June 1999 Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 2C15A Pad 180 PR12D 181 PR11A 182 PR11B 183 PR11C 184 PR11D 185 V SS 186 PR10A 187 PR10B ...
Page 104
ORCA Series 2 FPGAs Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 225 PR1D 226 V SS 227 RD_CFGN 228 V DD 229 V SS 230 V DD 231 V SS ...
Page 105
Data Sheet June 1999 Pin Information (continued) Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued) Pin 2C12A Pad 2C15A Pad 270 PT9A 271 V SS 272 PT8D 273 PT8C 274 PT8B 275 PT8A 276 PT7D 277 PT7C ...
Page 106
ORCA Series 2 FPGAs Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout Pin 2C/2T10A Pad 2C/2T12A Pad B1 PL1D PL1D C2 PL1C PL1C C1 PL1B PL1B D2 PL1A PL1A D3 PL2D PL2D D1 PL2C ...
Page 107
Data Sheet June 1999 Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad P4 PL9C PL10C P1 PL9B PL10B N3 PL9A PL10A R2 PL10D PL11D P3 PL10C PL11C R1 ...
Page 108
ORCA Series 2 FPGAs Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad AE3 — AF3 PB1B PB1B AE4 PB1C PB1C AD4 PB1D PB1D AF4 PB2A PB2A AE5 — ...
Page 109
Data Sheet June 1999 Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad AD13 PB9D PB10D AE15 PB10A PB11A AD14 PB10B PB11B AF15 PB10C PB11C AE16 PB10D PB11D AD15 ...
Page 110
ORCA Series 2 FPGAs Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad AC25 PR16B PR18B AC24 PR16C PR18C AC26 PR16D PR18D AB25 PR15A PR17A AB23 PR15B PR17B AB24 ...
Page 111
Data Sheet June 1999 Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad N24 PR7A PR8A M26 PR7B PR8B L25 PR7C PR8C M24 PR7D PR8D L26 PR6A PR7A M23 ...
Page 112
ORCA Series 2 FPGAs Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad A23 PT15D PT17D B22 PT15C PT17C D22 PT15B PT17B C22 PT15A PT17A A22 PT14D PT16D B21 ...
Page 113
Data Sheet June 1999 Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad A12 PT7B PT8B B11 PT7A PT8A C12 PT6D PT7D A11 PT6C PT7C D12 PT6B PT7B B10 ...
Page 114
ORCA Series 2 FPGAs Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad AC4 V SS AC8 V SS AD24 V SS AD3 V SS AE1 V SS AE2 ...
Page 115
Data Sheet June 1999 Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad T23 L11 ...
Page 116
... PL10D R30 PL10C R31 PL10B T29 PL10A Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected 116 2C/2T26A Pad 2C/2T40A/B Pad PL1D PL1D ...
Page 117
... AH30 PL20B AH29 PL20A AG28 CCLK Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected Lucent Technologies Inc. 2C/2T26A Pad 2C/2T40A/B Pad PL13D ...
Page 118
... PB10B AL17 PB10C AJ16 PB10D AH16 PB11A Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected 118 2C/2T26A Pad 2C/2T40A/B Pad PB1A PB1A ...
Page 119
... AJ4 PB20D AH5 DONE AG4 RESET Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected Lucent Technologies Inc. 2C/2T26A Pad 2C/2T40A/B Pad PB13B ...
Page 120
... PR11A U1 PR11B T3 PR11C T4 PR11D T2 PR10A Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected 120 2C/2T26A Pad 2C/2T40A/B Pad PRGM PRGM PR24A PR30A ...
Page 121
... D3 PR1D E4 RD_CFGN D5 PT20D C4 PT20C Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected Lucent Technologies Inc. 2C/2T26A Pad 2C/2T40A/B Pad PR12B PR15B PR12C ...
Page 122
... PT11A D16 PT10D B16 PT10C A17 PT10B Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected 122 2C/2T26A Pad 2C/2T40A/B Pad PT24B PT29B ...
Page 123
... V SS A16 Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected Lucent Technologies Inc. 2C/2T26A Pad 2C/2T40A/B Pad PT12A PT15A PT11D ...
Page 124
... Y31 A31 V DD Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected 124 2C/2T26A Pad 2C/2T40A/B Pad ...
Page 125
... U28 Notes: The OR2T15A pin AG2 is not connected in the 432-pin EBGA package. The pins labeled I/O-V 5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected Lucent Technologies Inc. 2C/2T26A Pad 2C/2T40A/B Pad ...
Page 126
Data Sheet June 1999 Package Thermal Characteristics There are three thermal parameters that are in com- mon use should be noted that all JA JC, and JC , the parameters are affected, to varying degrees, by package design ...
Page 127
Data Sheet June 1999 Package Thermal Characteristics FPGA Maximum Junction Temperature Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed ...
Page 128
ORCA Series 2 FPGAs Package Parasitics (continued) These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capaci- tances in pF are listed the mutual capacitance of the lead to the nearest neighbor lead; ...
Page 129
Data Sheet June 1999 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...
Page 130
... Standby Current: DDSB OR2C04A/OR2T04A OR2C06A/OR2T06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A/OR2T12A OR2C15A/OR2T15A OR2C26A/OR2T26A OR2C40A/OR2T40A I Standby Current: DDSB OR2C04A/OR2T04A OR2C06A/OR2T06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A/OR2T12A OR2C15A/OR2T15A OR2C26A/OR2T26A OR2C40A/OR2T40A V Data Retention Voltage DR C Input Capacitance IN C Output Capacitance OUT R DONE Pull-up Resistor* DONE R M3, M2, M1, and M0 M Pull-up Resistors* ...
Page 131
Data Sheet June 1999 Electrical Characteristics Table 31B. OR2TxxB Electrical Characteristics OR2TxxB Commercial 3 3 °C DD Parameter Symbol Input Voltage: V High V Low Output Voltage: V High Low I ...
Page 132
ORCA Series 2 FPGAs Timing Characteristics Table 32A. OR2CxxA and OR2TxxA Combinatorial PFU Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter Combinatorial ...
Page 133
Data Sheet June 1999 Timing Characteristics (continued) A[4:0], B[4:0] A[4:0], B[4:0] A[4:0], B[4:0] C0MUX_DEL, C0XOR_DEL, C0ND_DEL controlled by configuration RAM. Notes: The parameters MUX_DEL, XOR_DEL, and ND_DEL include the delay through the LUT in F5A/F5B modes. See ...
Page 134
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 33A. OR2CxxA and OR2TxxA Sequential PFU Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter ...
Page 135
Data Sheet June 1999 Timing Characteristics (continued) Table 33B. OR2TxxB Sequential PFU Timing Characteristics OR2TxxB Commercial 3 3 °C DD +85 °C. Parameter Input Requirements Clock Low Time Clock High Time Global S/R Pulse ...
Page 136
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 34A. OR2CxxA and OR2TxxA Ripple Mode PFU Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD ...
Page 137
Data Sheet June 1999 Timing Characteristics (continued) Table 34B. OR2TxxB Ripple Mode PFU Timing Characteristics OR2TxxB Commercial 3 3 °C DD +85 °C. Parameter Ripple Setup Times ( ° min): ...
Page 138
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C ...
Page 139
Data Sheet June 1999 Timing Characteristics (continued) Table 36A. OR2CxxA and OR2TxxA Asynchronous Memory Write Characteristics (MA/MB Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C ...
Page 140
ORCA Series 2 FPGAs Timing Characteristics (continued) A[3:0], B[3:0] C0 (WPE) MEM*_WPESET A4, B4 (WREN) WD[3:0] 140 T WC MEM*_APWRSET T PW MEM*_AWRSET MEM*_DPWRSET MEM*_DWRSET Figure 57. Write Operation June 1999 MEM*_PWRAHLD MEM*_WPEHLD MEM*_WRAHLD MEM*_PWRDHLD MEM*_WRDHLD 5-3228(F).r6 Lucent Technologies Inc. ...
Page 141
Data Sheet June 1999 Timing Characteristics (continued) Table 37A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write Operation (MA/MB Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3.6 V, ...
Page 142
ORCA Series 2 FPGAs Timing Characteristics (continued) A[3:0], B[3:0] CO (WPE) A4, B4 (WREN) DATA STABLE DURING WREN AND WPE WD[3:0] F[3:0] WD[3:0] DATA CHANGING DURING WREN AND WPE F[3:0] 142 T PW MEM*_PWRDEL MEM*_WRDEL MEM*_PWRDEL MEM*_WRDEL Figure 58. Read ...
Page 143
Data Sheet June 1999 Timing Characteristics (continued) Table 38A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write, Clocking Data into Latch/ Flip-Flop (MA/MB Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3.0 ...
Page 144
ORCA Series 2 FPGAs Timing Characteristics (continued) A[3:0], B[3:0] C0 (WPE) A4, B4 (WREN) WD[3:0] CK Q[3:0] Figure 59. Read During Write—Clocking Data into Flip-Flop 144 MEM*_ASET MEM*_PWRSET T PW MEM*_WRSET MEM*_DSET REG_DEL June 1999 5-3230(F).r6 Lucent Technologies Inc. ...
Page 145
Data Sheet June 1999 Timing Characteristics (continued) Table 39A. OR2CxxA and OR2TxxA Synchronous Memory Write Characteristics (SSPM and SDPM Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3.6 V, ...
Page 146
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes) (continued) OR2TxxB Commercial 3 3 °C DD Parameter Write Operation Setup Time: Address to Clock (A[3:0]/B[3:0] ...
Page 147
Data Sheet June 1999 Timing Characteristics (continued) Table 40A. OR2CxxA and OR2TxxA Synchronous Memory Read Characteristics (SSPM and SDPM Modes) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3.6 V, ...
Page 148
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 41A. OR2CxxA and OR2TxxA PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 ...
Page 149
... OR2C08A/OR2T08A CLK_DEL — OR2C10A/OR2T10A CLK_DEL — OR2C12A/OR2T12A CLK_DEL — OR2C15A/OR2T15A CLK_DEL — OR2C26A/OR2T26A CLK_DEL — OR2C40A/OR2T40A CLK_DEL — Notes: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input ...
Page 150
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 43A. OR2CxxA and OR2TxxA OR2CxxA/OR2TxxA Global Clock to Output Delay (Pin-to-Pin)—Output on Same Side of the Device as the Clock Pin OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD ...
Page 151
Data Sheet June 1999 Timing Characteristics (continued) Table 43B. OR2TxxB Global Clock to Output Delay (Pin-to-Pin)—Output on Same Side of the Device as the Clock Pin OR2TxxB Commercial 3 3 °C DD Industrial: V ...
Page 152
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 44A. OR2CxxA/OR2TxxA Global Clock to Output Delay (Pin-to-Pin)—Output Not on Same Side of the Device as the Clock Pin OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial: ...
Page 153
Data Sheet June 1999 Timing Characteristics (continued) . Table 44B. OR2TxxB Global Clock to Output Delay (Pin-to-Pin)—Output Not on Same Side of the Device as the Clock Pin OR2TxxB Commercial 3 3 °C DD ...
Page 154
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 45A. OR2CxxA/OR2TxxA Global Input to Clock Setup/Hold Time (Pin-to-Pin) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD ...
Page 155
Data Sheet June 1999 Timing Characteristics (continued) Table 45B. OR2TxxB Global Input to Clock Setup/Hold Time (Pin-to-Pin) OR2TxxB Commercial 3 3 °C DD Description Device (T = all all Input ...
Page 156
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 46A. OR2CxxA/OR2TxxA Programmable I/O Cell Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter Inputs ...
Page 157
Data Sheet June 1999 Timing Characteristics (continued) . Table 46B. OR2TxxB Programmable I/O Cell Timing Characteristics OR2TxxA Commercial 3 3 °C DD +85 °C. Parameter Inputs ( ° min) J ...
Page 158
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 47. Series 2 General Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD –40 ...
Page 159
Data Sheet June 1999 Timing Characteristics (continued) Table 47. Series 2 General Configuration Mode Timing Characteristics (continued) OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD ...
Page 160
ORCA Series 2 FPGAs Timing Characteristics (continued) Series PRGM INIT CCLK M[3:0] DONE Figure 65. General Configuration Mode Timing Diagram 160 INIT_CLK T HMODE T SMODE T CL June ...
Page 161
Data Sheet June 1999 Timing Characteristics (continued) Table 48. Series 2 Master Serial Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD ...
Page 162
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 49. Series 2 Master Parallel Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD ...
Page 163
Data Sheet June 1999 Timing Characteristics (continued) Table 50. Series 2 Asynchronous Peripheral Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD ...
Page 164
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter ...
Page 165
Data Sheet June 1999 Timing Characteristics (continued) Table 52A. OR2CxxA/OR2TxxA Slave Serial Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter ...
Page 166
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 53A. OR2CxxA/OR2TxxA Slave Parallel Configuration Mode Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD Parameter ...
Page 167
Data Sheet June 1999 Timing Characteristics (continued) Table 54. Series 2 Readback Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA/B Commercial 3 3 °C DD –40 °C T ...
Page 168
ORCA Series 2 FPGAs Timing Characteristics (continued) Table 55. Series 2 Boundary-Scan Timing Characteristics OR2CxxA Commercial 5.0 V ± 5%, 0 °C DD OR2TxxA Commercial 3 3 °C DD OR2TxxB Commercial: V ...
Page 169
Data Sheet June 1999 Measurement Conditions TO THE OUTPUT UNDER TEST A. Load Used to Measure Propagation Delay OUT[I] OUT[I] PAD OUT Lucent Technologies Inc THE OUTPUT UNDER TEST B. Load Used to Measure Rising/Falling Edges Figure ...
Page 170
Data Sheet June 1999 Output Buffer Characteristics OR2CxxA OUTPUT VOLTAGE, V Figure 77. Sinklim ( ° 250 225 200 175 150 125 100 75 ...
Page 171
ORCA Series 2 FPGAs Output Buffer Characteristics OR2TxxA 0.0 0.5 1.0 OUTPUT VOLTAGE, V Figure 83. Sinklim (T 140 120 100 0.0 0.5 1.0 OUTPUT VOLTAGE, ...
Page 172
Data Sheet June 1999 Output Buffer Characteristics OR2TxxB 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE, V Figure 89. Sinklim ( ° 180 160 140 ...
Page 173
Data Sheet June 1999 Package Outline Drawings Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. ...
Page 174
ORCA Series 2 FPGAs Package Outline Drawings 84-Pin PLCC Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 1.27 TYP 174 (continued) 30.353 MAX 29.083 0.076 1 0.330/0.533 June 1999 75 74 29.083 0.076 30.353 MAX 54 ...
Page 175
Data Sheet June 1999 Package Outline Drawings 100-Pin TQFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 100 DETAIL A 0.50 TYP 1.00 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A Lucent Technologies Inc. (continued) 16.00 0.20 ...
Page 176
ORCA Series 2 FPGAs Package Outline Drawings 144-Pin TQFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 144 DETAIL A 0.50 TYP 1.00 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A 176 (continued) 22.00 0.20 20.00 0.20 ...
Page 177
Data Sheet June 1999 Package Outline Drawings 160-Pin QFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 160 DETAIL A 0.65 TYP 1.60 REF GAGE PLANE SEATING PLANE Lucent Technologies Inc. (continued) 31.20 ± 0.20 28.00 ± ...
Page 178
ORCA Series 2 FPGAs Package Outline Drawings 208-Pin SQFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP 1.30 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A 178 (continued) 30.60 ± 0.20 28.00 ...
Page 179
Data Sheet June 1999 Package Outline Drawings 208-Pin SQFP2 Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 208 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP (SEE DETAIL C) DETAIL A 0.50 TYP 1.30 ...
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ORCA Series 2 FPGAs Package Outline Drawings 240-Pin SQFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 240 DETAIL A 0.50 TYP 1.30 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A 180 (continued) 34.60 ± 0.20 32.00 ...
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Data Sheet June 1999 Package Outline Drawings 240-Pin SQFP2 Dimensions are in millimeters. 34.60 32.00 24. 2 REF PIN #1 IDENTI FIER ZONE 240 EXPOSED HEAT SINK APPEARS ON TOP SURFACE IN CHIP FACE-DOWN VERSION OR BOTTOM ...
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ORCA Series 2 FPGAs Package Outline Drawings 256-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.36 0.60 0. CENTER ARRAY ...
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Data Sheet June 1999 Package Outline Drawings 304-Pin SQFP Dimensions are in millimeters. 304 PIN #1 IDENTIFIER ZONE DETAIL A 0.50 TYP 1.30 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A Lucent Technologies Inc. (continued) 42.60 ± ...
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ORCA Series 2 FPGAs Package Outline Drawings 304-Pin SQFP2 Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 304 EXPOSED HEAT SINK APPEARS ON TOP SURFACE IN CHIP FACE-DOWN VERSION OR BOTTOM SURFACE IN CHIP FACE-UP VERSION DETAIL ...
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Data Sheet June 1999 Package Outline Drawings 352-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.56 0.60 0. ...
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ORCA Series 2 FPGAs Package Outline Drawings 432-Pin EBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE 0.91 0.06 0.63 0. BALL CORNER 186 ...
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Data Sheet June 1999 Ordering Information Example: DEVICE TYPE SPEED GRADE OR2C12A, -4 speed grade, 240-pin shrink quad flat pack, commercial temperature. Table 56. FPGA Voltage Options Device OR2CxxA OR2TxxA OR2TxxB Table 57. FPGA Temperature Options Symbol Description (Blank) Commercial ...
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ORCA Series 2 FPGAs Ordering Information (continued) Table 59. ORCA OR2CxxA/OR2TxxA Series Package Matrix 84-Pin 100-Pin Packages PLCC TQFP M84 T100 OR2C/2T04A CI CI OR2C/2T06A CI CI OR2C/2T08A CI — OR2C/2T10A CI — OR2C/2T12A CI — OR2C/2T15A CI — OR2C/2T26A ...
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ORCA Series 2 FPGAs Index A Absolute Maximum Ratings, 129 Adder (see LUT Operating Modes) Architecture Overview, 5 PLC, 22 PIC Bidirectional Buffers (BIDIs), 14, 17, 18, 20, 22 (see also Routing and SLIC) Bit Stream (see FPGA ...
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Data Sheet June 1999 Index (continued) 160-Pin QFP, 177 208-Pin SQFP, 178 208-Pin SQFP2, 179 240-Pin SQFP, 180 240-Pin SQFP2, 181 256-Pin PBGA, 182 304-Pin SQFP, 183 304-Pin SQFP2, 184 352-Pin PBGA, 185 432-Pin EBGA, 186 Terms and Definitions, 173 ...
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Data Sheet June 1999 Notes Lucent Technologies Inc. ORCA Series 2 FPGAs 191 ...
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For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro or for FPGA information, http://www.lucent.com/orca E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In ...