SPCA711A ETC, SPCA711A Datasheet
SPCA711A
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SPCA711A Summary of contents
Page 1
... SPCA711A automatically detects the input data formats (PAL/NTSC, CCIR601) and switches internally to provide the proper format on the outputs. This feature, along with the on-board voltage reference and single clock interface, makes the SPCA711A extremely simple to use. In addition, use of 2x over-sampling on-chip simplifies external filter design resulting in reduced overall system cost. ...
Page 2
... Vertical sync input/output. VSYNC is latched/output following the rising edge of CLK. I/O Horizontal sync input/output. rising edge of CLK. I Master/slave mode selection. operation. A logical 0 for slave mode operation and Cb pixel sequence configuration pin. A logic high swap the SPCA711A CLKOUT DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ...
Page 3
... Composite/Luminance output. This is a high-impedance current source output. The output format can be selected by the PAL pin. CVBSY can drive a 37.5 O Composite/Chroma output. This is a high impedance current source Output. The output format can be selected by the PAL pin. The pin can drive a 37.5 load. SPCA711A Description load. The ...
Page 4
... Type - Analog power pin - Analog ground pin PIN Description MODEA YCSWAP EFIELD SPCA711A Description If the master mode is MODEB PALSA PAL625 ...
Page 5
... Cb and Cr order can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing. If the pixel stream input to the SPCA711A is off by one CLK period, the SPCA711A can lock to the pixel stream by setting the YCSWAP register. This will prevent Y and Cr/Cb pixels from swapping. ...
Page 6
... Pixel transitions must occur observing setup and hold timing about the rising edge of CLK. (3). Pixel sequence will beging with Cbn clock periods following the falling edge of HSYNC*, when integer. Cbn Yn Crn Crn Yn Cbn SPCA711A Cbn Crn+2 ...
Page 7
... Color burst is disabled on appropriate scan lines. Active pixels Total Pixels 720 x 240 858 x 262 720 x 288 864 x 313 Horizontal Start of Burst (c) Sync Width ( SPCA711A CLK Frequency (MHz Duration of Burst ( Back porch (e) 127 ...
Page 8
... For PAL- color burst information is automatically disabled on scan lines 1-6, 310-318, and 623-625, inclusive, for fields and 6. During fields and 8, color burst information is disabled on scan lines 1-5, 311-319, and 622-625, inclusive. " For example, 525-line operation is assumed, 625-line operation is detected by SPCA711A The horizontal counter is ...
Page 9
... DACs are powered down. When returned to low, the device starts from a reset state (horizontal and vertical counters = 0, which is the start of VSYNC in Field 1). This mode should be set when the SPCA711A is subjected to clock frequencies outside its functional range. If Master = 1, the HSYNC* and VSYNC* pins remain driven to the value of previous output before SLEEP was activated ...
Page 10
... Start of YSYNC Burst Phase 265 266 267 268 269 Burst Phase 265 266 267 268 269 0 Relative to B-Y 0 Relative to B-Y SPCA711A 270 271 272 270 271 272 22 285 22 285 ...
Page 11
... Field 3 624 625 Analog Field 4 312 313 314 315 316 Field One Field Two Field Three Field Four 0 Relative 225 Relative to U SPCA711A 317 318 319 320 317 318 319 320 23 24 336 337 ...
Page 12
... Field 7 624 625 Analog Field 8 312 313 314 315 316 Field Five Field Six Field Seven Field Eight 0 Relative 225 Relative to U SPCA711A 317 318 319 320 317 318 319 320 23 24 336 337 ...
Page 13
... Min. TA -40 GND-0.5 TS -65 TJ Min SPCA711A Tpy. Max. 4.5 +125 VAA+0.5 +150 +150 Tpy. Max. 3.3 3.6 -- +70 37.5 -- 1.27 Limit Min Typ Max 3 ...
Page 14
... =2.4V) IOH =0.8V) IOL VREFOUT IREFOUT For PAL- and Nc the standard blanking level is SPCA711A 20 2.0 VAA+0.5 GND-0 ...
Page 15
... A well-designed power distribution network is critical to eliminate digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for ground and power, respectively. SPCA711A ...
Page 16
... COMPONENT PLACEMENT Components should be placed as close as possible to the associated pin. The optimum layout enables the SPCA711A to be located as close as possible to the power supply connector and the video output connector. ! POWER AND GROUND PLANES For optimum performance, a common digital and analog ground plane is recommended. Separate digital and analog power planes are recommended ...
Page 17
... Analog Power Plane Mod LPF Schottky Diodes To Filter Schottky Diodes 22pF 75 1 330pF 270pF SPCA711A +3.3V (VCC) C1 Ground (Power Supply Connector) To Video Connector Buffer Regulated + Modulator (1) ZIN = 1K Audio ...
Page 18
... Ferrite Bead(z < 300 @ 5MHz) RESET 1% Metal Film Resistor TRAP Ceramic Resonator Schottky Diodes Note: Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect SPCA711A performance. " Description Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743021447 ATC LCB0805, Taiyo Yuden BK2125LM182 Dale CMF-55C Murata TPSx ...
Page 19
... PACKAGE INFORMATION Model Number SPCA711A NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product # Package Ambient Temperature Range 32-pin PLCC SPCA711A 0- 70 ...
Page 20
... Min. Typ. Max. 0.1 - 0.14 0.06 - 0.09 0.013 - 0.02 0.026 - 0.03 0.485 - 0.49 0.447 - 0.45 0.39 - 0.43 0.585 - 0.59 0.547 - 0.55 0.49 - 0. SPCA711A mm Min. Typ. 2.54 - 1.52 - 0.33 - 0.66 - 12.3 - 11.3 - 9.91 - 14.8 - 13 Max. 3.56 2.41 0.53 0.81 12.57 11.56 10 ...