SH66P20A Sino Wealth Microelectronic, SH66P20A Datasheet

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SH66P20A

Manufacturer Part Number
SH66P20A
Description
Manufacturer
Sino Wealth Microelectronic
Datasheet

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SH66P20A
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Features
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General Description
SH66P20A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 1K program ROM, Timer
and I/O Port.
Pin Configuration
SH6610C-based single-chip 4-bit microcontroller
ROM: 1K X 16 bits
RAM: 64 X 4 bits (Data memory)
Operation voltage: 2.4V - 6.0V (Typical 3.0V or 5.0V)
12 CMOS bi-directional I/O pins
4-level subroutine nesting (including interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power on reset
Powerful interrupt sources:
- Internal interrupt (Timer0)
- External interrupts: PortB & PortC (Falling edge)
PORTA.2
PORTA.3
PORTB.0
PORTB.1
PORTB.2
PORTB.3
RESET
GND
T0
1
2
3
4
5
6
7
8
9
1
Oscillator (user option)
- X`tal oscillator:
- Ceramic resonator:
- RC oscillator:
- External clock: 30K ~ 4MHz
Instruction cycle time:
- 4/32.768KHz (≈ 122us) for 32.768KHz OSC clock
- 4/4MHz (= 1us) for 4MHz OSC clock
Two low power operation modes: HALT and STOP
OTP type
Code protection
Built-in watchdog timer
18
17
16
15
14
13
12
11
10
PORTA.1
PORTA.0
OSCI
OSCO
V
PORTC.3
PORTC.2
PORTC.1
PORTC.0
DD
OTP 4-bit Microcontroller
32.768KHz ~ 4MHz
400K ~ 4MHz
400K ~ 4MHz
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SH66P20A
V2.3

SH66P20A Summary of contents

Page 1

... Warm-up timer for power on reset Powerful interrupt sources: - Internal interrupt (Timer0) - External interrupts: PortB & PortC (Falling edge) General Description SH66P20A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 1K program ROM, Timer and I/O Port. Pin Configuration www.DataSheet4U.com Oscillator (user option) ...

Page 2

... Bit programmable I/O, Vector Interrupt (Active falling edge) I/O Bit programmable I/O, Vector Interrupt (Active falling edge) P Power supply pin O OSC output pin. There is a signal with a frequency of Fosc/4 for RC mode OSC input pin can be connected to crystal﹑ceramic or external resistor I I/O Bit programmable I/O 2 SH66P20A RESET CPU PORTA [3:0] PORTB [3:0] PORTC [3:0] Description ...

Page 3

... Decimal adjust for addition/subtraction (DAA, DAS) Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) 2. ROM The SH66P20A can address up to 1024 X 16 bit of program area from $000 to $3FF. Service routine such as starting vector address. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address ...

Page 4

... PA1OUT PA0OUT W Set PORTA to be output port PB1OUT PB0OUT W Set PORTB to be output port PC1OUT PC0OUT W Set PORTC to be output port - - - Reserved. T0S T0E W Bit0: T0 signal edge, Bit1: T0 signal source - - - Reserved - - W Bit3: WDT time-out bit (write one only Reserved 4 SH66P20A Remarks ...

Page 5

... V DD LPD > LPD : LPD detect voltage about 1.9 ± 0.3V Bit1 Bit0 R/W LPD Enable Control (LPD3 ~ 0): LPD0 W 1010: LPD Enable (Default); 0101: LPD Disable LPD Enable/Disable flag. Enable LPD circuit (Power-on initial). Disable LPD circuit. 5 SH66P20A Remark ...

Page 6

... I/O Ports The SH66P20A provides 12 I/O pins. When every I/O is used as an input port, the port control register controls ON/OFF of the output buffer. Sections below show the circuit configuration of I/O ports. Each of these ports contains 4 bits I/O pins. ON/OFF of the output buffer for port can be controlled by the port control register. ...

Page 7

... And further falling edge transition would not be able to make interrupt request until all of the pins return to V Following is the port interrupt function block-diagram. PORTC.3 PC3OUT PORTC.2 PC2OUT PORTC.1 PC1OUT PORTC.0 PC0OUT PORTB.3 PB3OUT PORTB.2 PB2OUT PORTB.1 PB1OUT PORTB.0 PB0OUT DD FALLING EDGE PORT DETECTION INTERRUPT 7 SH66P20A to GND will generate ...

Page 8

... The input clock of watchdog timer is generated by a built-in RC oscillator,so that the WDT will always run even in the STOP mode. SH66P20A generates a RESET condition when watchdog times-out. Watchdog can be enabled or disabled permanently by user option. To prevent it from timing out and generating a device RESET condition, one can write this bit as "1" before timing-out ...

Page 9

... RC OSC = 5V): Prescaler divide ratio 1:1 1:2 1:4 1:8 1:32 1:128 1:512 1:2048 (Power on initial) WDT Time out Period Internal 7ms PRESCALER TM0 SCALER_1 / Final WDT Time OUT period 9 SH66P20A Timer-out period 7ms 14ms 28ms 56ms 224ms 896ms 3,584ms 14,336ms /32 /128 /512 /2048 ...

Page 10

... Timer0 SH66P20A has one 8-bit timer. The time/counter has the following features: . 8-bit timer/counter . Readable and writable . Automatic reloadable counter . 8-prescaller scale is available . Internal and external clock select . Interrupt on overflow from $FF to $00 . Edge select for external event Following is a simplified timer block diagram: ...

Page 11

... OSC ∆ osc ∆ osc Δ ∆ ≥ OSC Δ OSC N 11 SH66P20A Ratio N 512 128 When prescaler ratio selects /20, T0C is the OSC ...

Page 12

... However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated. Bit1 Bit0 - IEP - IRQP 2 3 Instruction Instruction Execution Execution I1 I2 Vector Generated Fetch Vector address Interrupt Accepted Stacking Reset IE.X 12 SH66P20A Remarks Interrupt enable flags Interrupt request flags 4 5 Start at vector address ...

Page 13

... DD C1, C2 < 10p ( C1, C2 Setting : Ceramic 400KHz : 20p < C1, C2 < 470p (V Ceramic 20p < C1, C2 < 150p (V 400K ~ 4MHz Ceramic 4MHz : 20p < C1, C2 < 100p (V C1, C2 < 10p ( Fosc/4 External clock source 13 SH66P20A = 5V 3V 5V); DD ...

Page 14

... Initial State Hardware Program counter CY Data memory System register AC Timer counter Timer load register WDT counter WDT prescaler I/O Ports T0S T0E WDT LPD After power on reset $000 Undefined Undefined Undefined Undefined Input 00 0 1010 14 SH66P20A ...

Page 15

... AC, Mx ← ← AC, Mx ← AC, Mx ← Mx ⊕ I AC, Mx ← AC, Mx ← Mx & I Function AC; Mx ← Decimal adjustment for add. AC; Mx ← Decimal adjustment for sub. 15 SH66P20A Flag Change Flag Change CY ...

Page 16

... X (Not including p) PC ←ST; TBR ← hhhh; PC ← llll AC CY; PC ← ST ← X (Include p) PC ← (PC11-PC8) (TBR) (AC Operation I Immediate data ⊕ Logical exclusive OR | Logical OR & Logical AND bbb RAM bank = 000 TBR Table Branch Register 16 SH66P20A Flag Change Flag Change CY ...

Page 17

... V - 0.7 DD GND + 0.6 17 SH66P20A periods may affect device Condition V All output pins unloaded (Execute NOP instruction) All output pins unload, WDT off LPD off (If WDT on 20µA) SB1 SB1 All output pins unload, WDT off ...

Page 18

... WDT ∆ F/F 1 PPM ∆ F/F 10 PPM ∆ F/F 0.1 % ∆ F ∆ F/F 7 SH66P20A Condition X’tal osc = 32.768KHz Ceramic Osc = 400KHz RC Osc = 400KHz WDT RC oscillator = 1/18ms Hz Crystal oscillator: [F(5.0) - F(4.5)]/F(5.0) Crystal oscillator 30P Ceramic resonator Oscillator: [F(5.0) - F(4.5)]/F(5.0) Include supply voltage and chip to chip variation RC oscillator: [F(-10°C) - F(60°C)]/F(-10°C) ...

Page 19

... F(2.7)]/F(3. Include supply voltage and chip to chip variation 7 oscillator:[F(-10°C) - F(60°C)]/F(-10°C) 19 SH66P20A = 4MHz [external clock], unless otherwise specified) Condition V All output pins unloaded (Execute NOP instruction) All output pins unload, WDT off LPD off (If WDT on 8µA) ...

Page 20

... T0 RC OSCO Timing Waveform RC - OSC PORT OSCO - RC Built-in RC Oscillator RESET OSC WDT Built-in RC Min. Typ. Max. 1 122 (T + 40)/ TiwL Tiw Tosc1 (Tosc2, Tosc3) 20 SH66P20A Unit Condition µ Prescaler divide ratio Twdt ...

Page 21

... Typical RC oscillator Resistor vs. Frequency: (V 10000 100 0 Typical RC oscillator Resistor vs. Frequency 10000 100 0 = 3V, for reference only) DD 200 400 600 800 1000 1200 1400 1600 1800 R (K Ω 5V, for reference only 200 400 600 800 1000 1200 1400 1600 1800 R (K Ω SH66P20A ...

Page 22

... Application Circuits (for reference only) AP1: a. Operating voltage: 3.0V. b. Oscillator: Crystal 32.768KHz. c. PORTA - C: I/O. AP2: a. Operating voltage: 5.0V. b. Oscillator: Crystal 4MHz. c. PORTA - C: I/O. 33KΩ PA.0 PA.1 PC.0 PA.2 PC.1 PA.3 PC.2 PB.0 PC.3 PB.1 PB.2 RESET PB.3 T0 OSCI V DD OSCO GND 47KΩ I/O PA.0 PA.1 PC.0 PA.2 PC.1 PA.3 PC.2 PB.0 PC.3 PB.1 PB.2 RESET PB.3 T0 OSCI V DD OSCO GND 22 SH66P20A I/O 47K 20p 20p I/O 47KΩ 20p 20p ...

Page 23

... Oscillator: Ceramic 400KHz. c. PORTA - C: I/O. AP4: a. Operating voltage: 5.0V. b. Oscillator: RC 400KHz. c. PORTA – C: I/O. d. Timer0 input: T0. 47KΩ 33KΩ PA.0 PA.1 PC.0 PA.2 PC.1 PA.3 PC.2 PB.0 PC.3 PB.1 PB.2 PB.3 RESET 22KΩ T0 OSCI V DD OSCO GND PA.0 I/O PA.1 PC.0 PA.2 PC.1 PA.3 PC.2 PB.0 PC.3 PB.1 PB.2 PB.3 RESET T0 OSCI V DD OSCO GND 23 SH66P20A I/O 47KΩ 0.1µ 100p 100p I/O 47KΩ 470KΩ 1000p ...

Page 24

... AP5: Reset Protection Circuit 1 RESET will be pulled to GND when V AP6: Reset Protection Circuit 2 RESET will be pulled to GND when ( 33K 10K RESET 40K goes lower than Zener voltage + 0.7V 10K RESET 40K R2 X R1/(R1 + R2)) is lower than 0. SH66P20A ...

Page 25

... X Y Pad No. 677.60 12 677.60 13 691.20 14 558.75 15 415.75 16 283.30 17 161.40 18 26.40 19 -224.10 20 -397.70 21 -675.65 25 SH66P20A OSCO V DD 1520µm 15 PORTC.3 14 PORTC.2 PORTC.1 13 Designation X PORTC.0 577.95 PORTC.1 664.60 PORTC.2 664.60 PORTC.3 664.60 V 627.30 DD OSCO 625.40 OSCI 422.45 GND 290 PORTA ...

Page 26

... Larger package size and in tray packing Larger package size and in tube packing L B Larger package size and in tape & reel packing T Smaller package size and in tray packing Smaller package size and in tube packing S N Smaller package size and in tape & reel packing 26 SH66P20A Packing Tube Tube ...

Page 27

... Typ. (0.262 Max.) 6.35 Typ. (6.65 Max.) 1 0.100 ± 0.010 1 L 0.130 ± 0.010 α 0° ~ 15° 0.345 ± 0.035 A S 0.055 Max. does not include resin fins SH66P20A unit: inches/ α A Dimension in mm 4.45 Max. 0.25 Min. 3.30 ± 0.25 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 7.62 ± 0.25 2.54 ± ...

Page 28

... NOM. 1 0.406 ± 0.012 E L 0.030 ± 0.008 0.055 ± 0.008 E S 0.037 Max. y 0.004 Max. θ 0° ~ 10° is for PC Board surface mount pad pitch design 1 28 SH66P20A unit: inches/ θ L Detail 2.79 Max. 0.10 Min. 2.33 ± 0.13 0.41 +0.10 -0.05 0.25 +0.10 -0.05 11.56 ± 0.38 7.49 ± ...

Page 29

... Data Sheet Revision History Version 2.3 Add package and packing information in ordering information 2.2 Change RC Frequency Variation to ±20% 2.1 Add Reset Protection Circuit (AP5 and AP6) 1.0 Original Content 29 SH66P20A Date Jul. 2004 Apr. 2002 Feb. 2002 Jun. 2000 ...

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