IW4042BD Integral Corp., IW4042BD Datasheet

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IW4042BD

Manufacturer Part Number
IW4042BD
Description
Quad cloced D latch, high-voltage silicon-gate CMOS
Manufacturer
Integral Corp.
Datasheet

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common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p-channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are
present. When a CLOCK transition occurs (positive for
POLARITY = 0 and negative for POLARTY = 1) the information
present at the input during the CLOCK transition is retained at
the outputs until an opposite CLOCK transition occurs.
line ceramic packages (D and F suffixes); 16-lead dual-in-line
plastic package (E suffix), and in chip form (H suffix).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
CD4042B types contain four latch circuits, each strobed by a
The CD4042B types are supplied in 16-lead hermetic dual-in-
LOGIC DIAGRAM
PIN 8 = GND
PIN 16 =V
Q
UAD
High-Voltage Silicon-Gate CMOS
CC
C
LOCKED
IW4042B
1
«D» L
POLARITY
ATCH
CLOCK
Clock
PIN ASSIGNMENT
0
1
GND
1
0
ORDERING INFORMATION
Q4
Q1
Q1
D1
D2
FUNCTION TABLE
Inputs
T
A
= -55° to 125° C for all
1
2
3
4
5
6
7
8
IW4042BN Plastic
IW4042BD SOIC
Polarity
packages
0
0
1
1
16
15
14
13
12
11
10
9
V CC
Q4
D4
D3
Q3
Q3
Q2
Q2
Outputs
Latch
Latch
Q
D
D

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IW4042BD Summary of contents

Page 1

... V min @ 10.0 V supply 2.5 V min @ 15.0 V supply LOGIC DIAGRAM PIN 16 =V PIN 8 = GND IW4042B C «D» L UAD LOCKED High-Voltage Silicon-Gate CMOS CC 1 ATCH ORDERING INFORMATION IW4042BN Plastic IW4042BD SOIC T = -55° to 125° C for all A packages PIN ASSIGNMENT ...

Page 2

MAXIMUM RATINGS Symbol Parameter V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin I P Power Dissipation in ...

Page 3

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Symbol Parameter V Minimum High- IH Level Input Voltage V Maximum Low - IL Level Input Voltage V Minimum High- OH Level Output Voltage V Maximum Low- OL Level Output Voltage I Maximum Input ...

Page 4

AC ELECTRICAL CHARACTERISTICS(C Symbol Parameter t , Maximum Propagation Delay, Clock to PLH t Q (Figure 1) PHL t , Maximum Propagation Delay, Clock to PLH t Q (Figure 1) PHL t , Maximum Propagation Delay, Data to Q PLH ...

Page 5

IW4042B Figure 1. Switching Waveforms Figure 2. Switching Waveforms 5 ...

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