IS62C1024L-70TI Integrated Silicon Solution, IS62C1024L-70TI Datasheet

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IS62C1024L-70TI

Manufacturer Part Number
IS62C1024L-70TI
Description
Manufacturer
Integrated Silicon Solution
Datasheet
IS62C1024L
128K x 8 LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 150 µW (typical) CMOS
• Output Enable (OE) and two Chip Enable
• Fully static operation: no clock or refresh
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
standby
(CE1 and CE2) inputs for ease in applications
required
I/O0-I/O7
A0-A16
VDD
GND
CE1
CE2
WE
OE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
CMOS static RAM. It is fabricated using
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
ISSI
MEMORY ARRAY
IS62C1024L is a low power,131,072-word by 8-bit
COLUMN I/O
128K x 8
ISSI
DECEMBER 2003
ISSI
's high-performance
®
1

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IS62C1024L-70TI Summary of contents

Page 1

... CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C1024L is available in 32-pin plastic SOP and TSOP (type 1) packages. DECODER MEMORY ARRAY I/O ...

Page 2

... IS62C1024L PIN CONFIGURATION 32-Pin SOP VDD A16 2 31 A15 A14 3 30 CE2 WE A12 A13 ISSI 62C1024L A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A16 ...

Page 3

... IS62C1024L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 4

... IS62C1024L POWER SUPPLY CHARACTERISTICS Symbol Parameter I V Dynamic Operating CC DD Supply Current I TTL Standby Current 1 SB (TTL Inputs) I CMOS Standby 2 SB Current (CMOS Inputs) Note address and data inputs are cycling at the maximum frequency means no input lines change. ...

Page 5

... IS62C1024L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC TEST LOADS 480 5V OUTPUT 255 100 pF Including jig and scope Figure 1a. AC WAVEFORMS (1,2) READ CYCLE NO. 1 ADDRESS DOUT Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 6

... IS62C1024L (1,3) READ CYCLE NO. 2 ADDRESS OE CE1 CE2 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = V 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time ...

Page 7

... IS62C1024L AC WAVEFORMS WE Controlled WRITE CYCLE NO. 1 (WE ADDRESS CE1 CE2 DOUT DATA UNDEFINED DIN CE1, CE2 Controlled) CE1 CE1 CE1 WRITE CYCLE NO. 2 (CE1 ADDRESS t SA CE1 CE2 WE DOUT DATA UNDEFINED DIN Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...

Page 8

... IS62C1024L DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR DATA RETENTION WAVEFORM (CE1 VDD 4.5V 2. CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) VDD 4.5V CE2 2. 0.4V GND ...

Page 9

... IS62C1024L-70Q 70 IS62C1024L-70T Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 35 IS62C1024L-35QI 35 IS62C1024L-35TI 70 IS62C1024L-70QI 70 IS62C1024L-70TI Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 Package Plastic SOP TSOP, Type 1 Plastic SOP TSOP, Type 1 Package Plastic SOP TSOP, Type 1 Plastic SOP TSOP, Type 1 Integrated Silicon Solution, Inc ...

Page 10

... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

Page 11

... REF Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

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