ST10F168 SGS-Thomson-Microelectronics, ST10F168 Datasheet
ST10F168
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ST10F168 Summary of contents
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... DIRECT OR PRESCALED CLOCK INPUT 111 GENERAL PURPOSE I/O LINES – INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION. – PROGRAMMABLE THRESHOLD (HYSTERESIS) IDLE AND POWER DOWN MODES 144-PIN PQFP PACKAGE ARBITRATION FLASH Interrupt controller P.0 P.1 P.4 P.6 P.5 ST10F168 PRELIMINARY DATA RAM CPU Core Watchdog PEC OSC BRG BRG P.7 P.8 P.3 1/76 ...
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... ST10F168 TABLE OF CONTENTS 1 INTRODUCTION ......................................................................................................... 2 PIN DATA ................................................................................................................... 3 FUNCTIONAL DESCRIPTION.................................................................................... 4 MEMORY ORGANIZATION........................................................................................ 5 FLASH MEMORY ................................................................................... .................... 5.1 PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL .......... 5.2 PROGRAMMING EXAMPLES .................................................................................... 5.3 FLASH MEMORY CONFIGURATION......................................................................... 5.4 FLASH PROTECTION ............................... ................................................................. 5.5 BOOTSTRAP LEADER MODE ................................................................................... 6 CENTRAL PROCESSING UNIT (CPU) ...................................................................... 6.1 INSTRUCTION SET SUMMARY................................................................................. 7 EXTERNAL BUS CONTROLLER............................................................................... 8 INTERRUPT SYSTEM ................................................................................................ ...
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... Direct Drive................................................................................................................. 20.5.6 Oscillator Watchdog (OWD) ........................................................................................ 20.5.7 Phase Locked Loop..................................................................................................... 20.5.8 External Clock Drive XTAL1....................... ................................................................. 20.5.9 Memory Cycle Variables.......................................................................... .................... 20.5.10 Multiplexed Bus ............................................................. .............................................. 20.5.11 Demultiplexed Bus....................................................................................................... 20.5.12 CLKOUT and READY.............................................................................. .................... 20.5.13 External Bus Arbitration............................................................................................... 21 PACKAGE MECHANICAL DATA ................................ .............................................. 22 ORDERING INFORMATION ....................................................................................... ST10F168 ...
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... ST10F168 1 - INTRODUCTION The ST10F168 is a derivative of the ST Microelec- tronics 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high Figure 1 : Logic Symbol XTAL1 XTAL2 RSTIN RSTOUT AREF V AGND NMI EA READY ALE RD WR/WRL Port 5 16-bit 4/76 peripheral functionality and enhanced I/O capabil- ities ...
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... P7.7/CC31I0 27 P5.0/AN0 28 P5.1/AN1 29 P5.2/AN2 30 P5.3/AN3 31 P5.4/AN4 32 P5.5/AN5 33 P5.6/AN6 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 ST10F168 ST10F168 108 P0H.0/AD8 107 P0L.7/AD7 106 P0L.6/AD6 105 P0L.5/AD5 104 P0L.4/AD4 103 P0L.3/AD3 102 P0L.2AD2 101 P0L.1/AD1 100 P0L.0/AD0 ALE ...
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... ST10F168 Table 1 : Pin Description Symbol Pin Type P6 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The following Port 6 pins have alternate functions: ...
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... ASC0 Clock / Data Output (Asynchronous / Synchronous) RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous) BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe SCLK SSC Master Clock Output / Slave Clock Input CLKOUT System Clock Output (=CPU Clock) ST10F168 7/76 ...
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... External Access Enable pin. A low level at this pin during and after Reset forces the ST10F168 to start the program in internal memory space. A high level forces the ST10F168 to start in the external memory space. P0L.0 - P0L.7 100 - 107, I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or P0H ...
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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F168 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode. ...
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... Byte Flash memory 6K Byte XRAM CAN_RxD P4.5 CAN CAN_TxD P4 Port 6 8 10/76 The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F168. 32 CPU-Core 16 PEC 16 Interrupt Controller BRG BRG Port 5 Port 7 Port Internal ...
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... MEMORY ORGANIZATION The memory space of the ST10F168 is configured in a Von Neumann architecture. Code memory, data memory, registers and I/O ports are orga- nized within the same linear address space of 16M Byte. The entire memory space can be accessed bytewise or wordwise. Particular por- tions of the on-chip memory have additionally been made directly bit addressable ...
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... ST10F168 Figure 4 : ST10F168 on-chip memory mapping 0x14 0x5’0000 0x4’FFFF 0x13 0x4’C000 0x12 0x4’8000 0x11 0x4’4000 Bank 3 : 96K Byte 0x10 0x4’0000 0x0F 0x3’C000 0x0E 0x3’8000 0x3’7FFF 0x0D 0x3’4000 0x0C 0x3’0000 0x0B 0x2’ ...
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... Flash continues as nor- mal. The first bank (16K Byte) and part of the second bank (16K Byte out of 48K Byte) of the on-chip Flash Memory of the ST10F168 can be mapped to either segment 0 (addresses 00000h to 07FFFh segment 1 (addresses 10000h to 17FFFh) during the initialization phase. External memory can be used for additional system flexibility ...
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... ST10F168 5.1 - Programming / Erasing with ST Embedded Algorithm Kernel There are three stages to run STEAK : – To load the registers with the STEAK command, the address and the data to be pro- gramed, or sector to be erased. Table 4 gives the STEAK parameters for each type of Flash programming / erasing operation ...
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... ACCOUNT THE FACT THAT STEAK USES WORDS ON THE SYS- TEM STACK. ABNORMAL SITUATION VERY IMPORTANT RECTLY THE STACK SIZE TO AT LEAST 64 WORDS, AND TO CORRECTLY INI- TIALIZE REGISTER STKOV. ST10F168 R3 R4-R15 Data in Flash for Unchanged location Segment + Segment Offset + 2 (R0[3:0] with R1+2) Unchanged ...
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... ST10F168 5.2 - Programming Examples Programming a double Word ; code shown below assumes that Flash is mapped in segment 1 ; ie. bit ROMS1 = ‘1’ in SYSCON register ; Flash must be enabled, ie. bit ROMEN = ‘1’ in SYSCON. MOV R0, #0DD40h ; DD4xh : Double Word programming command OR R0, #01h ; Selects segment 1 in flash memory ...
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... R7 used for Flash trigger sequence #define FCR 08000h EXTS # Flash can be mapped in segment MOV FCR first part MOV [R7 second part NOP ; WARNING: place 2 NOP operations after NOP ; the Unlock sequence to avoid all possible ; pipeline conflicts in STEAK programs POP DPP2 ; restore DPP2 ST10F168 17/76 ...
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... Pin P0L.4 (BSL) activates the on-chip bootstrap loader, when low during hardware reset. The bootstrap loader allows moving the start code into the internal RAM of the ST10F168 via the serial interface ASC0. The ST10F168 will remain in bootstrap loader mode until a hardware reset with P0L ...
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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F168’s instructions can be exe- cuted in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bit to be shifted ...
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... ST10F168 6.1 - Instruction Set Summary The Table 8 lists the instructions of the ST10F168. The various addressing modes, instruction opera- tion, parameters for conditional execution of Table 8 : Instruction set summary Mnemonic ADD(B) Add Word (Byte) operands ADDC(B) Add Word (Byte) operands with Carry SUB(B) Subtract Word (Byte) operands ...
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... EINIT Signify End-of-Initialization on ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence EXTS(R) Begin EXTended Segment (and Register) sequence NOP Null operation Description RSTOUT -pin ST10F168 Bytes ...
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... ST10F168 7 - EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four dif- ferent external memory access modes : – 24-bit addresses and 16-bit data, demultiplexed. – ...
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... Software interrupts are sup- ported by means of the ‘TRAP’ instruction in com- bination with an individual trap (interrupt) number. to the Table 9 shows all the available ST10F168 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Request ...
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... ST10F168 Table 9 : Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 ...
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... NMITRAP 00’0008h STOTRAP 00’0010h STUTRAP 00’0018h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h [2Ch –3Ch] Any [00’0000h– 00’01FCh] in steps of 4h ST10F168 Trap Number Trap Priority 00h III 00h III 00h III 02h II 04h II 06h II 0Ah I 0Ah I 0Ah ...
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... ST10F168 9 - CAPTURE / COMPARE (CAPCOM) UNIT The ST10F168 has two 16 channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform ...
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... CC3 CC4 CC5 CC6 CC7 1 1 CC8 CC9 2.3 2.4 2.5 2.6 2.7 2.8 2 8.3 8.4 8.5 8.6 8.7 1H.4 1H 132 133 ST10F168 101 110 111 256 512 1024 97.7KHz 48.8KHz 24.4KHz 10.24 s 20.48 s 40.96 s 671ms 1.34s 2.68s CC12 CC13 CC14 CC15 CC10 CC11 2.10 2.11 2.12 2.13 2.14 2.15 59 ...
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... ST10F168 10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer / counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...
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... Timer Input Selection T5I / T6I 001B 010B 011B 100B 640ns 1.28 s 2.56 s 41.9ms 83.9ms 167ms U/D GPT1 Timer T2 Reload Capture GPT1 Timer T3 U/D Capture Reload GPT1 Timer T4 U/D ST10F168 101B 110B 111B 128 256 512 5.12 s 10.24 s 20.48 s 336ms 671ms 1.34s Interrupt Request T3OUT T3OTL Interrupt Request Interrupt Request 29/76 ...
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... ST10F168 Figure 7 : Block Diagram of GPT2 T5EUD CPU Clock T5 2n n=2...9 Mode T5IN Control CAPIN T6 T6IN Mode CPU Clock 2n n=2...9 T6EUD 30/76 U/D GPT2 Timer T5 Clear Capture GPT2 CAPREL Reload Toggle FF T60TL GPT2 Timer T6 U/D Interrupt Request Interrupt Request Interrupt Request T6OUT to CAPCOM Timers ...
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... PPx Period Register * Match Comparator * PTx Up/Down/ 16-Bit Up/Down Counter Clear Control Match Comparator Output Control Shadow Register Write Control * PWx Pulse Width Register ST10F168 14-bit 16-bit 1.526KHz 0.381KHz 23.84Hz 5.96Hz 14-bit 16-bit 762.9Hz 190.7Hz 11.92Hz 2.98Hz POUTx Enable 31/76 ...
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... ST10F168 12 - PARALLEL PORTS The ST10F168 provides up to 111 I/O lines organized into eight input / output ports and one input port. All port lines are bit-addressable, and all input / output lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...
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... For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The AD converter of the ST10F168 supports dif- ferent conversion modes : – Single channel single conversion : the analog level of the selected channel is sampled once and converted ...
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... ST10F168 14 - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning ...
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... The High-Speed Synchronous Serial Interface SSC provides flexible high-speed communication between the ST10F168 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode received from an external master (slave mode) ...
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... ST10F168 15 - CAN MODULE The integrated CAN module completely handles the autonomous transmission and the reception of CAN frames according to the CAN specification V2.0 part B (active). The on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...
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... This starting location will typically point to the gen- eral initialization routine. Timing of asynchronous reset sequence are summarized in Figure CPU Clock Latching point of Port0 for systemstart-up configuration ST10F168 Conditio ns > 1032 TCL < 1032 TCL RSTIN pin must be held at low PP INST #1 ...
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... ST10F168 17.2 - Synchronous Reset (Warm Reset) A synchronous reset is triggered when RSTIN pin is pulled low while V pin is at high level. In order PP to properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low ...
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... This bidirectional reset function is useful in appli- cations where external devices require a reset signal but cannot be connected to RSTOUT pin. This is the case of an external memory running codes before EINIT ( end of initialization) instruc- tion is executed. RSTOUT pin is pulled high only when EINIT is executed. ST10F168 2), CPU XTAL 39/76 ...
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... A. If bit PWDCFG of SYSCON register is set, an internal pullup resistor is activated at the end of the reset sequence. This pullup will charge any capacitor connected on V pin. The simplest way to reset the ST10F168 is to insert a capacitor C1 between RSTIN pin and V and a capacitor between V pin and V PP ...
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... Reset The minimum reset circuit of Figure 14 is not ade- quate when the RSTIN pin is driven from the ST10F168 itself during software or watchdog trig- gered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V end of the internal reset sequence, and thus will triggered an asynchronous reset sequence ...
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... ST10F168 Figure 14 : System Reset Circuit RSTOUT RSTIN ST10F168 42/76 External Hardware D1 External o.d. Reset Source Open Drain Inverter ...
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... All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. ST10F168 mode: this 43/76 ...
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... ST10F168 19 - SPECIAL FUNCTION REGISTER OVERVIEW Table 22 lists all SFRs which are implemented in the ST10F168 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
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... CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 ST10F168 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...
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... ST10F168 Table 22 : Special Function Registers listed by name Physical 8-bit Name address address CC29IC b F184h E C2h CC30 FE7Ch 3Eh CC30IC b F18Ch E C6h CC31 FE7Eh 3Fh CC31IC b F194h E CAh CCM0 b FF52h A9h CCM1 b FF54h AAh CCM2 b FF56h ABh CCM3 b FF58h ACh CCM4 b FF22h ...
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... PWM Module Up / Down Counter 2 PWM Module Up / Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 ST10F168 Reset value 0000h 00h 00h 00h FFFF h ...
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... ST10F168 Table 22 : Special Function Registers listed by name Physical 8-bit Name address address PWMIC b F17Eh E BFh RP0H b F108h E 84h S0BG FEB4h 5Ah S0CON b FFB0h D8h S0EIC b FF70h B8h S0RBUF FEB2h 59h S0RIC b FF6Eh B7h S0TBIC b F19Ch E CEh S0TBUF FEB0h 58h S0TIC b FF6Ch ...
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... Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL unlock Interrupt Control Register Constant Value 0’s Register (read only) ST10F168 Reset value 0000h 0000h 0000h 0000h 0000h ...
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... ST10F168 19.1 - Identification Registers The ST10F168 has four Identification registers, mapped in ESFR space. These register contain: – A manufacturer identifier, – A chip identifier, with its revision, – A internal memory and size identifier, – Programming voltage description. IDMANUF (F07Eh / 3Fh MANUF ...
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... DD defined by the Absolute Maximum Ratings. 20.2 - Parameter Interpretation The parameters listed in the following tables represent the characteristics of the ST10F168 and its demands on the system. Where the ST10F168 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the “Symbol” column. ...
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... ST10F168 Symbol Parameter 1 Output high voltage (Port0, Port1, Port4, ALE RD, WR, BHE, CLKOUT, RSTOUT Output high voltage (all other outputs) OH1 I CC Input leakage current (Port 5) OZ1 I CC Input leakage current (all other) OZ2 I SR Overload current ...
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... Notes 1. ST10F168 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column “ ...
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... ST10F168 20.4 - A/D Converter Characteristics 10 0V, 4. -40, +85 C and for Q2 version TA = -40 C, +125 C, unless otherwise specified A Symbol Parameter V SR Analog input voltage range AIN Sample time Conversion time C TUE CC Total unadjusted error R SR Internal resistance of reference voltage source ...
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... For timing purposes a port pin is no longer floating when V It begins to float when a 100mV change from the loaded V 20.5.2 - Definition of Internal Timing The internal operation of the ST10F168 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. ...
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... ST10F168 Figure 18 : Generation Mechanisms for the CPU Clock Phase locked loop operation f XTAL f CPU Direct Clock Drive f XTAL f CPU Prescaler Operation f XTAL f CPU 20.5.3 - Clock Generation Modes The Table 23 associates the combinations of these three bit with the respective clock generation mode. Table 23 : CPU Frequency Generation P0H ...
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... CPU individual TCL. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. ST10F168 and increments the Interrupt Request = f x F). With every CPU XTAL ...
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... ST10F168 The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f CPU locked The relative deviation of TCL is XTAL the maximum when it is refered to one TCL period. It decreases according to the formula and to the Figure 19 given below. For N periods of ...
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... C – – – – – ST10F168 Values TCL x <ALECTL> 2TCL x (15 - <MCTC>) 2TCL <MTTC>) = 100pF, L Variable CPU Clock 1/2 TCL = 1 to 25MHz Unit Min. Max. – – – – ...
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... ST10F168 Table 24 : Multiplexed bus characteristics (continued) Symbol Parameter t CC Data valid Data hold after ALE rising edge after RD Address / Unlatched CS hold 27 after RD ALE falling edge to Latched Latched CS low to Valid Data In 39 ...
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... BUS (P0) RD Write Cycle Address BUS (P0) WR WRL WRH Address Data Data Out ST10F168 Address 61/76 ...
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... ST10F168 Figure 22 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE CLKOUT t 5 ALE CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) Address RD Write Cycle BUS (P0) Address WR WRL WRH 62/ Address t 7 Data In ...
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... A23-A16 (A15-A8) BHE t 6 Read Cycle Address BUS (P0) RdCSx t Write Cycle BUS (P0) Address WrCSx Address Data Data Out ST10F168 Address 63/76 ...
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... ST10F168 Figure 24 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE, read/write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) Address RdCSx Write Cycle BUS (P0) WrCSx 64/ Address ...
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... – TCL - 10 - – ( – > – ST10F168 = L Variable CPU Clock 1/2 TCL = 1 to 25MHz Unit Min. Max. – – – – – – – ...
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... ST10F168 Table 25 : Demultiplexed bus characteristics (continued) Symbol Parameter t SR Latched CS low to Valid Data Latched CS hold after RD Address setup to RdCS, WrCS 82 (with RW-delay Address setup to RdCS, WrCS 83 (no RW-delay RdCS to Valid Data In (with RW-delay RdCS to Valid Data In (no RW-delay) ...
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... Read Cycle Data Bus (P0 Write Cycle Data Bus (P0 WRL WRH 41u Address t 18 Data Data Out ST10F168 67/76 ...
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... ST10F168 Figure 26 : External Memory Cycle: demultiplexed bus, with / without read/write delay, extended ALE CLKOUT t 5 ALE CSx t 6 A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RD Write Cycle Data Bus (P0) WR WRL WRH 68/ Address ...
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... CLKOUT t 5 ALE A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0 RdCsx Write Cycle Data Bus (P0 WrCSx Address t 51 Data Data Out ST10F168 69/76 ...
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... ST10F168 Figure 28 : External Memory Cycle: demultiplexed bus, no read/write delay, extended ALE, read/write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RdCsx Write Cycle Data Bus (P0) WrCSx 70/ Address Data Out ...
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... – 4 – 54 – 2TCL + – – refers to the current bus cycle. F ST10F168 = L Variable CPU Clock 1/2 TCL = 1 to 25MHz Unit Min. Max. 2TCL 2TCL ns TCL – 6 – ns TCL – 10 – ns – – ...
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... ST10F168 Figure 29 : CLKOUT and READY Running cycle CLKOUT ALE RD, WR Synchronous READY t t Asynchronous 58 59 READY 3) Notes 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...
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... HLDA BREQ CSx (P6.x) Others Notes 1. The ST10F168 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pullup) after = -40, +85 C and for Q2 version TA = -40, +125 Max. CPU Clock ...
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... Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F168 requesting the bus. 2. The next ST10F168 driven bus cycle may start here. ...
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... Temperature range - - 125 C ST10F168 Inches (approx) Typ. Max. 0.160 0.133 0.144 0.015 0.009 1.228 1.238 1.102 1.106 0.896 0.026 1.228 1.238 1.102 1.106 0.031 0.037 0.063 Package ...
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... ST10F168 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice ...