PSD813F2 SGS-Thomson-Microelectronics, PSD813F2 Datasheet
PSD813F2
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PSD813F2 Summary of contents
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... Erase/WRITE Cycles of PLD June 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 3.0 PSD813F2/3/4/5, PSD833F2 PSD834F2, PSD853F2, PSD854F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs Figure 1. 52-pin, Plastic, Quad, Flat Package Figure 2 ...
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PSD8XXF2/3/4/5 TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PSD8XXF2/3/4/5 MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PSD8XXF2/3/4/5 DC AND AC PARAMETERS ...
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Figure 47. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... PSD8XXFX in as little as seven seconds. The innovative PSD8XXFX family solves key problems faced by designers when managing dis- crete Flash memory devices, such as: Table 1. Product Range (Note 1) Primary Flash Part Number Memory (8 Sectors) PSD813F2 1 Mbit PSD813F3 1 Mbit PSD813F4 1 Mbit PSD813F5 1 Mbit PSD833F2 ...
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KEY FEATURES A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a READ or WRITE is performed. ...
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PSD8XXF2/3/4/5 Figure 3. PSD8XXFX Block Diagram 10/103 AI02861E ...
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PSD8XXFX ARCHITECTURAL OVERVIEW PSD8XXFX devices contain several major func- tional blocks. Figure 3 shows the architecture of the PSD8XXFX device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions ...
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PSD8XXF2/3/4/5 JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD8XXFX device. A blank device can be com- pletely programmed. The JTAG signals (TMS, ...
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DEVELOPMENT SYSTEM The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD8XXFX design is quickly and easily produced in a point and click environment. The de- signer does not need to enter Hardware Descrip- tion ...
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PSD8XXF2/3/4/5 PIN DESCRIPTION Table 5 describes the signal names and signal functions of the PSD8XXFX. Table 5. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address ...
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Pin Name Pin Type These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O – write to or read from a standard output or input port. PA0 29 2. CPLD ...
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PSD8XXF2/3/4/5 Pin Name Pin Type PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read from a standard output or input port. 2. CPLD macrocell (McellBC5) ...
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Table 6. I/O Port Latched Address Output Assignments (Note1) MCU 8051XA (8-bit) N/A 80C251 (page mode) N/A All other 8-bit multiplexed Address a3-a0 8-bit non-multiplexed bus N/A Note: 1. See the section entitled “I/O PORTS”, on page 48, on how ...
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PSD8XXF2/3/4/5 DETAILED OPERATION As shown in Figure 3, the PSD8XXFX consists of six major types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG Interface The functions of each block are described ...
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Table 8. Instructions FS0-FS7 or CSBOOT0- Instruction CSBOOT3 “READ” READ Read Main AAh X555h Flash ID Read Sector AAh@ 1 6,8,13 X555h Protection Program a AAh X555h Flash Byte Flash Sector ...
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... READ operation, address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropri- ate Sector Select (FS0-FS7) must be High. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. Read Memory Sector Protection Status. The primary Flash memory Sector Protection Status is ...
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Reading the Erase/Program Status Bits. The PSD8XXFX provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends ...
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PSD8XXF2/3/4/5 Programming Flash Memory Flash memory must be erased prior to being pro- grammed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to 0. The MCU may erase Flash memory ...
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Data Toggle. Checking the Toggle Flag (DQ6) bit is a method of determining whether a Program or Erase cycle is in progress or has completed. Fig- ure 6 shows the Data Toggle algorithm. When the MCU issues a Program instruction, ...
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PSD8XXF2/3/4/5 Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruc- tion uses six WRITE operations followed by a READ operation of the status register, as de- scribed in Table 8. If any byte of the Bulk Erase in- ...
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... An Error condition has occurred (and the device has set the Error Flag (DQ5) bit to 1) during a Flash memory Program or Erase cycle. On the PSD813F2/3/4/5, the Reset Flash instruc- tion puts the Flash memory back into normal READ Mode. It may take the Flash memory few milliseconds to complete the Reset cycle ...
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PSD8XXF2/3/4/5 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The ...
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Memory Select Configuration for MCUs with Separate Program and Data Spaces. The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) ...
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PSD8XXF2/3/4/5 Combined Space Modes. The Data spaces are combined into one memory space that allows the primary Flash memory, sec- ondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) Figure 9. 8031 Memory Modules ...
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Page Register The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- PGR7) ...
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PSD8XXF2/3/4/5 PLDS The PLDs bring programmable logic functionality to the PSD8XXFX. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and avail- able upon Power-up. The PSD8XXFX contains ...
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Figure 11. PLD Diagram PORTS I/O BUS INPUT PLD PSD8XXF2/3/4/5 31/103 ...
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PSD8XXF2/3/4/5 Decode PLD (DPLD) The DPLD, shown in Figure 12, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: 8 Sector Select (FS0-FS7) signals for ...
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Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External ...
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PSD8XXF2/3/4/5 Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as ...
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Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ...
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PSD8XXF2/3/4/5 Figure 14. CPLD Output Macrocell 36/103 ARRAY AND BUS INPUT PLD ...
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The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Out- put Macrocells (OMC). The default ...
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PSD8XXF2/3/4/5 Figure 15. Input Macrocell 38/103 ARRAY AND BUS INPUT PLD ...
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Figure 16. Handshaking Communication Using Input Macrocells PSD8XXF2/3/4/5 39/103 ...
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PSD8XXF2/3/4/5 MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 15. The interface ...
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Figure 17. An Example of a Typical 8-bit Multiplexed Bus Interface MCU WR RD BHE ALE RESET 15:8 ] PSD8XXF2/3/4/5 PSD PORT A ( OPTIONAL ) ADIO PORT A ...
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PSD8XXF2/3/4/5 PSD8XXFX Interface to a Non-Multiplexed 8-Bit Bus. Figure 18 shows an example of a system us- ing a MCU with an 8-bit non-multiplexed bus and a PSD8XXFX. The address bus is connected to the ADIO Port, and the data ...
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MCU Bus Interface Examples Figure 19 to Figure 22 show examples of the basic connections between the PSD8XXFX and some popular MCUs. The PSD8XXFX Control input pins are labeled as to the MCU function for which they are configured. The ...
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PSD8XXF2/3/4/5 The first configuration is 80C31-compatible, and the bus interface to the PSD8XXFX is identical to that shown in Figure 19. The second and third con- figurations have the same bus connection as shown in Figure 18. There is only ...
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Figure 20. Interfacing the PSD8XXFX with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 ...
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PSD8XXF2/3/4/5 80C51XA. The Philips 80C51XA MCU family sup- ports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multi- plexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit ...
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Figure 22 shows a bus interface to a 68HC11 where the PSD8XXFX is configured in 8- bit multiplexed mode with E and R/W settings. The Figure 22. Interfacing the PSD8XXFX with a 68HC11 68HC11 ...
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PSD8XXF2/3/4/5 I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions ...
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The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the ...
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PSD8XXF2/3/4/5 Table 19. Port Operating Modes Port Mode MCU I/O Yes PLD I/O McellAB Outputs Yes McellBC Outputs No Additional Ext. CS Outputs No PLD Inputs Yes Address Out Yes (A7 – 0) Address In Yes Data Port Yes (D7 ...
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Table 21. I/O Port Latched Address Output Assignments MCU Port A (PA3-PA0) 1 8051XA (8-Bit) N/A 80C251 N/A (Page Mode) All Other Address a3-a0 8-Bit Multiplexed 8-Bit N/A Non-Multiplexed Bus Note: 1. N/A = Not Applicable. Address In Mode For ...
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PSD8XXF2/3/4/5 Port Configuration Registers (PCR) Each Port has a set of Port Configuration Regis- ters (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in ...
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Table 26. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port A Drain Drain Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note ...
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PSD8XXF2/3/4/5 Ports A and B – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure 25. The two ports can be configured to perform one or more of the following functions: MCU ...
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Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 26): MCU I/O Mode CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. ...
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PSD8XXF2/3/4/5 Port D – Functionality and Structure Port D has three I/O pins. See Figure 27 and Fig- ure 28. This port does not support Address Out mode, and therefore no Control Register is re- quired. Port D can be ...
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External Chip Select The CPLD also provides three External Chip Se- lect (ECS0-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product Figure 28. Port D External ...
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PSD8XXF2/3/4/5 POWER MANAGEMENT All PSD8XXFX devices offer configurable power saving options. These options may be used indi- vidually or in combinations, as follows: All memory blocks in a PSD8XXFX (primary and secondary Flash memory, and SRAM) are built with power ...
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Automatic Power-down (APD) Unit and Power- down Mode. The APD Unit, shown in Figure 29, puts the PSD8XXFX into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activ- ...
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PSD8XXF2/3/4/5 For Users of the HC11 (or compatible). The HC11 turns off its E clock when it sleeps. There- fore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power-down mode, you ...
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PLD Power Management The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in PMMR0. By setting the bit to 1, the Turbo mode is off and the PLDs con- sume the specified stand-by current ...
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PSD8XXF2/3/4/5 SRAM Standby Mode (Battery Backup). The PSD8XXFX supports a battery backup mode in which the contents of the SRAM are retained in the event of a power loss. The SRAM has Voltage Stand- PC2) that can be ...
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RESET TIMING AND DEVICE STATUS AT RESET Upon Power-up, the PSD8XXFX requires a Reset (RESET) pulse of duration t NLNH-PO steady. During this period, the device loads inter- nal configurations, clears some of the registers and sets the Flash memory ...
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PSD8XXF2/3/4/5 Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 and ...
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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface block can be enabled on Port C (see Table 34). All memory blocks (pri- mary and secondary Flash memory), PLD logic, and PSD8XXFX Configuration Register bits may be programmed ...
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PSD8XXF2/3/4/5 JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status ...
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AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD8XXFX: DC Electrical Specification AC Timing Specification PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing MCU Timing – READ ...
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PSD8XXF2/3/4/5 Figure 33. PLD I /Frequency Consumption (3 V range 68/103 = HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PT 100 ...
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Table 36. Example of PSD8XXFX Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number ...
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PSD8XXF2/3/4/5 Table 37. Example of PSD8XXFX Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode ...
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
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PSD8XXF2/3/4/5 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests ...
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Table 43. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input G Internal WDOG_ON signal I Interrupt Input L ALE Input N Reset Input or Output P Port Signal Output ...
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PSD8XXF2/3/4/5 Table 44. DC Characteristics (5V devices) Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) ...
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Table 45. DC Characteristics (3V devices) Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V ...
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PSD8XXF2/3/4/5 Figure 37. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 46. CPLD Combinatorial Timing (5V devices) Symbol Parameter CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output ...
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Figure 38. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Table 48. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f MAX Internal 1/(t Feedback (f ) CNT ...
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PSD8XXF2/3/4/5 Table 49. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f ) CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H ...
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Figure 39. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 40. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT tARPW tARP tCHA tCLA tSA tHA tCOA PSD8XXF2/3/4/5 AI02864 AI02859 79/103 ...
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PSD8XXF2/3/4/5 Table 50. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f Internal 1/(t MAXA SA Feedback (f ) CNTA Maximum Frequency 1/(t CHA Pipelined Data Input Setup t SA ...
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Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f MAXA Internal 1/(t Feedback (f ) CNTA Maximum Frequency 1/(t Pipelined Data Input Setup t SA Time t Input ...
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PSD8XXF2/3/4/5 Figure 41. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 52. Input Macrocell Timing (5V devices) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t ...
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Figure 42. READ Timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV Note and t are not required for 80C251 in Page Mode or ...
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PSD8XXF2/3/4/5 Table 54. READ Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV ...
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Table 55. READ Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD ...
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PSD8XXF2/3/4/5 Figure 43. WRITE Timing ALE /AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 86/103 t AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t ...
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Table 56. WRITE Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge ...
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PSD8XXF2/3/4/5 Table 57. WRITE Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading ...
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Table 58. Program, WRITE and Erase Times (5V devices) Symbol Flash Program 1 Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles ...
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PSD8XXF2/3/4/5 Figure 44. Peripheral I/O READ Timing ALE/AS A/D BUS CSI RD Table 60. Port A Peripheral Data Mode READ Timing (5V devices) Symbol Parameter Address Valid to Data t AVQV–PA Valid t CSI Valid to Data Valid SLQV–PA RD ...
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Table 61. Port A Peripheral Data Mode READ Timing (3V devices) Symbol Parameter t Address Valid to Data Valid AVQV–PA t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t ...
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PSD8XXF2/3/4/5 Figure 45. Peripheral I/O WRITE Timing ALE/ BUS WR Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices) Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation ...
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Figure 46. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Table 64. Reset (RESET) Timing (5V devices) Symbol Parameter t RESET Active Low Time NLNH t Power On Reset Active Low Time NLNH–PO t Warm ...
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PSD8XXF2/3/4/5 Figure 47. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 68. ISC Timing (5V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, ...
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Table 69. ISC Timing (3V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for t ISCCL PLD) t Clock (TCK, ...
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PSD8XXF2/3/4/5 PACKAGE MECHANICAL Figure 48. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 Figure 50. PQFP52 - 52-pin Plastic, ...
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Table 72. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0. ...
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PSD8XXF2/3/4/5 Figure 51. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 73. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ. A ...
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PART NUMBERING Table 74. Ordering Information Scheme Example: Device Type PSD8 = 8-bit PSD with Register Logic PSD9 = 8-bit PSD with Combinatorial Logic SRAM Capacity Kbit Kbit 5 = 256 Kbit Flash Memory ...
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PSD8XXF2/3/4/5 APPENDIX A. PQFP52 PIN ASSIGNMENTS Table 75. PQFP52 Connections (Figure 48) Pin Number Pin Assignments ...
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APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 76. PLCC52 Connections (Figure 49) Pin Number Pin Assignments ...
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PSD8XXF2/3/4/5 REVISION HISTORY Table 77. Document Revision History Date Rev. 15-Oct-99 1.0 Initial release as a WSI document 27-Oct-00 1.1 Port A Peripheral Data Mode Read Timing, changed to 50 30-Nov-00 1.2 PSD85xF2 added 23-Oct-01 2.0 Document rewritten using the ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...