MSM56V16800D-10 Oki Semiconductor, MSM56V16800D-10 Datasheet
MSM56V16800D-10
Related parts for MSM56V16800D-10
MSM56V16800D-10 Summary of contents
Page 1
... H version only. • CBR auto-refresh, Self-refresh capability • Package: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) PRODUCT FAMILY Max. Family Frequency MSM56V16800D-10 100 MHz 83 MHz MSM56V16800D-12 MSM56V16800DH-15 66 MHz This version: Mar. 1998 MSM56V16800D/DH (Product : MSM56V16800D/DH-xxTS-K) xx indicates speed rank. ...
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... Type) Pin Name DQM Data Input/Output Mask DQi Data Input/Output V Power Supply (3 Ground ( Data Output Power Supply (3 Data Output Ground ( Connection MSM56V16800D/ DQ8 DQ7 DQ6 DQ5 ...
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... Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal. DQi Data inputs/outputs are multiplexed on the same pin. MSM56V16800D/DH 3/30 ...
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... Decoders Buffers Latency I/O & Burst Controller Controller Input Data Register Column Decoders 9 Sense Amplifier 8 Read Data Register 8Mb Word Memory Drivers Cells 8Mb Word Memory Drivers Cells Sense Amplifier Column Decoders MSM56V16800D/DH Input Buffers Output DQ1 - Buffers DQ8 4/30 ...
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... opr *: Symbol Min 3 2 –0.3 IL Symbol Min IN1 C 2 IN2 C 2 OUT MSM56V16800D/DH (Voltages referenced to V Unit + 0 °C 600 °C (Voltages referenced Typ. Max. Unit 3.3 3.6 V — 0 0.8 — 3.3 V ±0 25° MHz) CC Max ...
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... IH CC — 90 CKE ≥ min min — CKE £ min IL CC — 2 CKE £ min IL CC — 2 MSM56V16800D/DH Version Unit Note D-12 DH-15 2.4 — 2.4 — V — 0.4 — 0 –10 10 – — 60 — — — ...
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... Enter the mode register setting command. Burst Length Sequential Interleave Reserved Reserved Reserved Reserved Reserved Reserved Full Page* : Not applicable to H version MSM56V16800D/ Reserved 7/30 ...
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... Data Output High Impedance Time from ROH CL > 1 Precharge Command Active Command Input Time from Mode l MRD Register Set Command Input (Min.) Write Command Input Time l OWD from Output MSM56V16800D-10 MSM56V16800D-12 MSM56V16800DH-15 Min. Max. Min. Max. 10 — 12 — 15 — 17.5 — 30 — ...
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... Notes : 1. AC measurements assume that t 2. The reference level for timing of input signals is 1 Output load. Output 4. The access time is defined at 1 longer than 1 ns, then the reference level for timing of input signals MSM56V16800D/ ns and IH 9/30 ...
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... Ca0 ADDR A11 Ra A10 DQM Row Active Read Command Qa0 Q a1 Qa2 Qa3 t OHZ t AC Row Active Write Command Precharge Command MSM56V16800D/ Cb0 Db0 Db1 Db2 Db3 t WR Precharge Command 10/30 ...
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... A11 BS BS A10 OLZ OHZ l OWD WE DQM Row Active Read Command High CCD Write Command Precharge Command Read Command MSM56V16800D/ 11/30 ...
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... After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. ) after DQM entry. OHZ MSM56V16800D/DH 12/30 ...
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... To assert row precharge before a burst write ends, wait t Input data during the precharge input cycle will be masked internally High Cc0 Cd0 Dc0 Dc1 Dd0 l t OWD WR *Note1 Write Command Write Command Precharge Command WR MSM56V16800D/ *Note2 after the last write data input. 13/30 ...
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... Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Qa0 Qa1 Qa2 A-Bank Precharge Start A Bank Read with Auto Precharge Row Active (B-Bank MSM56V16800D/ Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 ...
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... RBb CBb RAc RBb RAc QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 Read Command (B-Bank) Precharge Command (B-Bank) Precharge Command Row Active (A-Bank) (A-Bank) MSM56V16800D/ CAc QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) 15/30 ...
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... RBb CBb RAc RBb RAc DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 Row Active Precharge (B-Bank) Command (A-Bank) Write Command Row Active (B-Bank) (A-Bank) MSM56V16800D/ DAc0 DAc1 Write Command (A-Bank) Precharge Command (A-Bank) Precharge Command ...
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... High CBb CAc QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 Read Command (B-Bank) Read Command Read Command (B-Bank) (A-Bank) MSM56V16800D/ CBd CAe QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 l ROH Precharge Command (A-Bank) Read Command (A-Bank) 17/30 ...
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... RBb CBb CAc RAb DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 Row Active (B-Bank) Write Command Write Command (B-Bank) (A-Bank) MSM56V16800D/ CBd DBd0 Write Command (B-Bank) Precharge Command (Both Bank) ...
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... High RBb CBb RAc RBb RAc QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 Write Command (B-Bank) (B-Bank) Precharge Command Row Active (A-Bank) (A-Bank) MSM56V16800D/ CAc QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) 19/30 ...
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... CLK CKE CS RAS CAS CAa0 ADDR A11 A10 DQ QAa0 QAa1 WE DQM Read Command (A-Bank High CBb0 CAc0 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 Write Command Read Command (B-Bank) (A-Bank) MSM56V16800D/ QAc0 QAc1 QAc2 QAc3 20/30 ...
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... When DQM is asserted, the write data in the same clock cycle is masked *Note1 Qa1 Qa2 Qb0 t OHZ *Note2 CLOCK Read Suspension Command Read DQM MSM56V16800D/ *Note1 Qb1 Dc0 Dc2 t *Note3 OHZ Write Write Read DQM DQM DQM Write CLOCK Command Suspension 21/30 19 ...
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... In case CAS latency is 3, READ can be interrupted by WRITE. *Note: The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command Ca0 Da0 Da1 Da2 Da3 t WR Precharge Command Write Command MSM56V16800D/ 22/30 ...
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... Not applicable to H version High *Note1 Qa1 Qa2 Qa3 Qa4 Qa5 *Note2 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note2 Qa0 Qa1 Qa2 Qa3 Qa4 Precharge Command MSM56V16800D/ 23/30 ...
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... Power-down Entry *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800D/DH enters power-down mode and maintains the mode while CKE is low release the circuit from power-down mode, CKE has to be set high for longer than t ...
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... Semiconductor Self Refresh Cycle CLK CKE RAS CAS ADDR A11 A10 DQM Self Refresh Entry MSM56V16800D/ elf Row Refresh Active Exit 25/30 ...
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... Semiconductor Mode Register Set Cycle CLK High CKE CS l MRD RAS CAS ADDR DQM MRS New Command Auto Refresh Cycle High Auto Refresh MSM56V16800D/ Auto Refresh 26/30 ...
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... X BA RA, A10 ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge NOP (Continue Burst to End and enter Row Precharge ILLEGAL CA, A10 ILLEGAL ILLEGAL RA, A10 ILLEGAL ILLEGAL MSM56V16800D/DH Action 5 27/30 ...
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... X X NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL NOP = No OPeration command and t to prevent bus contention. CCD WR MSM56V16800D/DH Action RP RP RCD RCD RC RC 28/30 ...
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... MSM56V16800D/DH Action INVALID Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP (Continue power down mode) ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM56V16800D/DH (Unit : mm) Package material Epoxy resin ...